https://research.coe.drexel.edu/ece/vlsi/api.php?action=feedcontributions&feedformat=atom&user=Admin 2026-05-12T23:13:34Z User contributions MediaWiki 1.39.3 https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=8380 2025-08-26T13:10:22Z

<p>Admin: /* MS graduates */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> <br /> [[Scott Lerner]] (Ph.D 2024) [First job: Intel], Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;<br /> <br /> [[Michael Lui]] (ABD - First job: Meta)<br /> <br /> [[Ragh Kuttappa]] (Ph.D 2021) [First job: Intel], Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> <br /> Ceyhun Kayan (MS, 2025)<br /> <br /> Angela Wei (MS, 2021) [First job: SAP] Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Junghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> === Undergraduate Researchers ===<br /> <br /> Jonah Taylor (2024) [Drexel STARS scholar]<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> &lt;!--== Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> --&gt;<br /> <br /> === High-School Researchers ===<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=8379 2025-08-26T13:09:56Z

<p>Admin: /* Group Alumni */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> <br /> [[Scott Lerner]] (Ph.D 2024) [First job: Intel], Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;<br /> <br /> [[Michael Lui]] (ABD - First job: Meta)<br /> <br /> [[Ragh Kuttappa]] (Ph.D 2021) [First job: Intel], Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> <br /> [[Ceyhun Kayan]] (MS, 2025)<br /> <br /> Angela Wei (MS, 2021) [First job: SAP] Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Junghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> === Undergraduate Researchers ===<br /> <br /> Jonah Taylor (2024) [Drexel STARS scholar]<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> &lt;!--== Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> --&gt;<br /> <br /> === High-School Researchers ===<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=8378 2025-08-26T13:09:33Z

<p>Admin: /* Ph.D. Students */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> <br /> [[Scott Lerner]] (Ph.D 2024) [First job: Intel], Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;<br /> <br /> [[Michael Lui]] (ABD - First job: Meta)<br /> <br /> [[Ragh Kuttappa]] (Ph.D 2021) [First job: Intel], Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) [First job: SAP] Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Junghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> === Undergraduate Researchers ===<br /> <br /> Jonah Taylor (2024) [Drexel STARS scholar]<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> &lt;!--== Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> --&gt;<br /> <br /> === High-School Researchers ===<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7703 2025-01-19T19:47:18Z

<p>Admin: /* Journals */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024.<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5776 2021-06-30T00:37:45Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> Nicholas Sica<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) [First job: SAP] Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> <br /> === Undergraduate Researchers ===<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> &lt;!--== Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> --&gt;<br /> <br /> === High-School Researchers ===<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5771 2021-06-30T00:36:36Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> Nicholas Sica<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) [First job: SAP] Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> &lt;!--== Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> --&gt;<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5766 2021-06-30T00:35:41Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> Nicholas Sica<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> &lt;!--== Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> --&gt;<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) [First job: SAP] Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=5761 2021-06-30T00:34:01Z

<p>Admin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> # Ragh Kuttappa, Leo Fiippini, Nicholas Sica, Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=5756 2021-06-30T00:28:24Z

<p>Admin: /* Thesis and Dissertations */</p> <hr /> <div>== Conferences ==<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=5751 2021-06-30T00:27:16Z

<p>Admin: /* Thesis and Dissertations */</p> <hr /> <div>== Conferences ==<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> <br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2021<br /> <br /> <br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5746 2021-06-30T00:25:47Z

<p>Admin: /* MS graduates */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> Nicholas Sica<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) [First job: SAP] Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5741 2021-06-30T00:25:05Z

<p>Admin: /* Group Alumni */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> Nicholas Sica<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5736 2021-06-30T00:24:02Z

<p>Admin: /* Ph.D. Students */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> Nicholas Sica<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys, currently at LinkedIn], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel, Bangalore currently at Intel, OR], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5731 2021-06-30T00:23:27Z

<p>Admin: /* Group Alumni */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post-Doc, Intel], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys, currently at LinkedIn], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel, Bangalore currently at Intel, OR], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (MS, 2021) Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5726 2021-06-30T00:22:37Z

<p>Admin: /* Group Alumni */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Karthik Sangaiah]] (Ph.D. 2020) [First job: AMD Research], Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;<br /> <br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post Doctoral Researcher], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys, currently at LinkedIn], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel, Bangalore currently at Intel, OR], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Angela Wei (2021) Thesis: &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;<br /> <br /> [[Dongen Bradley Zhou]] (2021)<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=5721 2021-06-30T00:19:17Z

<p>Admin: /* Ph.D. Students */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> [[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> <br /> [[Ragh Kuttappa]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> == MS Students ==<br /> <br /> <br /> <br /> &lt;!--== MS Students ==<br /> --&gt;<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Malachi Moody (2020) [Delaware State University- NSF REU]}<br /> <br /> Eric Zane (2020) [Rowan University - NSF REU]}<br /> <br /> Angela Wei (2019) [Drexel]<br /> <br /> Steven Khoa (2019) [Drexel]<br /> <br /> Albert Emanuel Milani (2019) [Drexel, REU]<br /> <br /> Kathrina Waugh (2018) [Drexel STARS scholar]<br /> <br /> Rhea Dutta (2018) [Drexel STARS scholar]<br /> <br /> Neil Eelman (2018-2019) [Drexel]<br /> <br /> Irmak Gezginer (2017) [Middle East Technical University]<br /> <br /> Daniel Heuckeroth (2016) [Drexel STARS scholar]<br /> <br /> Albert Emanuel Milani (2016) [Drexel STARS scholar]<br /> <br /> Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]<br /> <br /> Brian Hosler (2015-2016) [Drexel]<br /> <br /> Eric Leggett, Jr (2015-2016) [Drexel]<br /> <br /> Gabrielle Madden (2015) [Drexel STARS scholar]<br /> <br /> Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]<br /> <br /> Eronides Felisberto Da Silva Neto (2015) [Temple]<br /> <br /> George Slavin (2015) [Drexel]<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel, MS at Penn]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)<br /> <br /> George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)<br /> <br /> David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ioannis A. Savidis (2019) [Undergraduate at Drexel University]<br /> <br /> Edison Kim (2016) [Undergraduate at Temple University]<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> === PhD graduates ===<br /> <br /> [[Vasil Pano]] (Ph.D. 2019) [First job: Post Doctoral Researcher], Dissertation: &quot;Wireless Network on Chip for Multi-Die Systems&quot;<br /> <br /> [[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: &quot;Charge Recovery Circuits&quot;<br /> <br /> [[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)<br /> <br /> [[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys, currently at LinkedIn], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel, Bangalore currently at Intel, OR], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> === MS graduates ===<br /> <br /> Steven Khoa (MS, 2020) [First job: There that must not be named] Thesis: &quot;Adiabatic Step-Charging Power-Clock Generator&quot;<br /> <br /> Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]<br /> <br /> Isikcan Yilmaz (MS, 2018) [First job: Apple]<br /> <br /> Stephen DeLuca (MS, 2015) [First job: Intel]<br /> <br /> Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]<br /> <br /> Swetha George (MS 2012) [Ph.D. at the University of Rochester]<br /> <br /> Kevin Daly (MS, 2011) [There that must not be named]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''<br /> <br /> === Visiting graduate students ===<br /> <br /> Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]<br /> <br /> Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]<br /> <br /> Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=3846 2019-01-11T15:33:33Z

<p>Admin: /* Curriculum Vitae */</p> <hr /> <div>[[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin]]|25px]]<br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering Department at Drexel University, Philadelphia, PA in 2005, where currently he is a Professor. Between 2003-2004, he was a PhD intern engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is the coauthor of the book entitled Timing Optimization Through Clock Skew Scheduling (Springer, 2009). He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015.<br /> <br /> He is from Izmir, Turkey. He graduated from Bornova Anatolian High School, Izmir, Turkey in 1993 and the Izmir Science High School, Izmir, Turkey in 1996. He is a lifeguard educator.<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Professor (2016-present)<br /> ; Associate Professor (2011-2016)<br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Staff Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> [http://vlsi.ece.drexel.edu/images/8/81/Taskin_CV.pdf CV (January 2019)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> '''Campus Location:'''<br /> &lt;br&gt; Office: Bossone Building 401<br /> &lt;br&gt; Lab: Bossone Building 405<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=MediaWiki:Sidebar&diff=1561 2016-09-05T21:07:10Z

<p>Admin: </p> <hr /> <div>* navigation<br /> ** mainpage|mainpage-description<br /> ** people|People<br /> ** research|Research<br /> ** publications|Publications<br /> ** software|Software<br /> ** seminars|Seminars<br /> ** tutorials|Tutorials<br /> ** teaching|Teaching<br /> ** news/Events|News/Events<br /> ** randompage-url|randompage<br /> * SEARCH<br /> * TOOLBOX<br /> * LANGUAGES</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=1430 2016-01-30T13:39:16Z

<p>Admin: /* Contact Info */</p> <hr /> <div>[[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin]]|25px]]<br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering at Drexel University, Philadelphia, PA, as an assistant professor in 2005, where currently he is an Associate Professor. Between 2003-2004, he was a staff engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is the coauthor of the book entitled Timing Optimization Through Clock Skew Scheduling (Springer, 2009). His research interests include Electronic Design Automation (EDA) for VLSI, low-power circuits, resonant clocking, clock network synthesis, wireless IC interconnects, Networks-on-Chip (NoC) for Chip Multi-Processors (CMPs), hardware/software design space exploration for exascale computing. He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015.<br /> <br /> He was born in Izmir, Turkey, in 1978. He graduated from Bornova Anatolian High School, Izmir, Turkey in 1993 and the Izmir Science High School, Izmir, Turkey in 1996. He is a lifeguard educator.<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Associate Professor (2011-present)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Staff Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (June 2015)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> '''Campus Location:'''<br /> &lt;br&gt; Office: Bossone Building 413F<br /> &lt;br&gt; Lab: Bossone Building 324<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=1429 2016-01-30T13:38:47Z

<p>Admin: /* Contact Info */</p> <hr /> <div>[[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin]]|25px]]<br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering at Drexel University, Philadelphia, PA, as an assistant professor in 2005, where currently he is an Associate Professor. Between 2003-2004, he was a staff engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is the coauthor of the book entitled Timing Optimization Through Clock Skew Scheduling (Springer, 2009). His research interests include Electronic Design Automation (EDA) for VLSI, low-power circuits, resonant clocking, clock network synthesis, wireless IC interconnects, Networks-on-Chip (NoC) for Chip Multi-Processors (CMPs), hardware/software design space exploration for exascale computing. He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015.<br /> <br /> He was born in Izmir, Turkey, in 1978. He graduated from Bornova Anatolian High School, Izmir, Turkey in 1993 and the Izmir Science High School, Izmir, Turkey in 1996. He is a lifeguard educator.<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Associate Professor (2011-present)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Staff Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (June 2015)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> '''Campus Location:'''<br /> &lt;br&gt; Office: Bossone Building 413F<br /> &lt;br&gt; Lab: Bossone Building 324<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=1428 2016-01-30T13:37:50Z

<p>Admin: /* Contact Info */</p> <hr /> <div>[[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin]]|25px]]<br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering at Drexel University, Philadelphia, PA, as an assistant professor in 2005, where currently he is an Associate Professor. Between 2003-2004, he was a staff engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is the coauthor of the book entitled Timing Optimization Through Clock Skew Scheduling (Springer, 2009). His research interests include Electronic Design Automation (EDA) for VLSI, low-power circuits, resonant clocking, clock network synthesis, wireless IC interconnects, Networks-on-Chip (NoC) for Chip Multi-Processors (CMPs), hardware/software design space exploration for exascale computing. He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015.<br /> <br /> He was born in Izmir, Turkey, in 1978. He graduated from Bornova Anatolian High School, Izmir, Turkey in 1993 and the Izmir Science High School, Izmir, Turkey in 1996. He is a lifeguard educator.<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Associate Professor (2011-present)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Staff Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (June 2015)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> &lt;br&gt; Office: Bossone Building 413F<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=MediaWiki:Sidebar&diff=1427 2016-01-30T13:32:17Z

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Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=1056 2014-06-15T15:58:59Z

<p>Admin: /* Design and Automation of Low Swing Clocking */</p> <hr /> <div>== CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Affiliated Faculty: Mark Hempstead (Computer Architecture)<br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Leo Filippini]]<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Affiliated Faculty: Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): [[Vasil Pano]], [[Leo Filippini]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (ECCS-1232164), Mosis<br /> <br /> Affiliated Faculty: Kapil Dandekar (Wireless Systems)<br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): [[Leo Filippini]]<br /> <br /> Sponsor(s): None<br /> <br /> Affiliated Faculty: Emre Salman SUNY-Stony Brook, Milutin Stanaćević, SUNY-Stony Brook (Circuits, Systems)<br /> <br /> = Previous Projects = <br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=1055 2014-06-15T15:33:37Z

<p>Admin: /* Ultra Low-Power Adiabatic Circuit Design */</p> <hr /> <div>== CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Affiliated Faculty: Mark Hempstead (Computer Architecture)<br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Leo Filippini]]<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Affiliated Faculty: Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): [[Vasil Pano]], [[Leo Filippini]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (ECCS-1232164), Mosis<br /> <br /> Affiliated Faculty: Kapil Dandekar (Wireless Systems)<br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): [[Leo Filippini]]<br /> <br /> Sponsor(s): None<br /> <br /> Affiliated Faculty: Emre Salman SUNY-Stony Brook, Milutin Stanaćević, SUNY-Stony Brook (Circuits, Systems)<br /> <br /> = Previous Projects = <br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=1054 2014-06-15T15:32:57Z

<p>Admin: </p> <hr /> <div>== CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Affiliated Faculty: Mark Hempstead (Computer Architecture)<br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Leo Filippini]]<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Affiliated Faculty: Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): [[Vasil Pano]], [[Leo Filippini]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (ECCS-1232164), Mosis<br /> <br /> Affiliated Faculty: Kapil Dandekar (Wireless Systems)<br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): [[Leo Filippini]]<br /> <br /> Sponsor(s): None<br /> <br /> Affiliated Faculty: Emre Salman SUNY-Stony Brook, Milutin Stanaćević, SUNY-Stony Brook<br /> <br /> = Previous Projects = <br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1053 2014-06-15T15:29:28Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> Julian Kemmerer, (MS, 2014) [First job: Susquehanna International Group]<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1052 2014-06-15T15:29:17Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> Julian Kemmerer, (MS, 2014) [First job: Susquehanna International Group]<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1051 2014-06-15T15:29:01Z

<p>Admin: /* Faculty */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> &lt;!-- Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)--&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> Julian Kemmerer, (MS, 2014) [First job: Susquehanna International Group]<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1050 2014-06-15T15:28:41Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> &lt;!== Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)==&gt;<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> Julian Kemmerer, (MS, 2014) [First job: Susquehanna International Group]<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1049 2014-06-15T15:25:42Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> == Affiliated Faculty ==<br /> <br /> Kapil Dandekar (Wireless Systems)<br /> <br /> Mark Hempstead (Computer Architecture)<br /> <br /> Ioannis Savidis (Circuits and Systems)<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> Julian Kemmerer, (MS, 2014) [First job: Susquehanna International Group]<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=1048 2014-06-15T15:18:26Z

<p>Admin: /* Wireless On-Chip Interconnects */</p> <hr /> <div>== CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Leo Filippini]]<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): [[Vasil Pano]], [[Leo Filippini]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (ECCS-1232164), Mosis<br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): [[Leo Filippini]]<br /> <br /> Sponsor(s): None<br /> <br /> <br /> <br /> = Previous Projects = <br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=1047 2014-06-15T15:17:57Z

<p>Admin: </p> <hr /> <div>== CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Leo Filippini]]<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): [[Leo Flippini]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (ECCS-1232164), Mosis<br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): [[Leo Filippini]]<br /> <br /> Sponsor(s): None<br /> <br /> <br /> <br /> = Previous Projects = <br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=1046 2014-06-15T15:10:39Z

<p>Admin: </p> <hr /> <div>== CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Leo Filippini]]<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): [[Leo Flippini]], [[Vasil Pano]], [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (ECCS-1232164), Mosis<br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Can Sitik]], [[Scott Lerner]], [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> = Previous Projects = <br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1045 2014-06-15T15:07:56Z

<p>Admin: /* Undergraduate Researchers */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Habeeb Olawin (2014) [Drexel STARS scholar]<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> Julian Kemmerer, (MS, 2014) [First job: Susquehanna International Group]<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1044 2014-06-15T15:04:04Z

<p>Admin: </p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> Julian Kemmerer, (MS, 2014) [First job: Susquehanna International Group]<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1043 2014-06-15T15:02:21Z

<p>Admin: /* Group Alumni */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Julian Kemmerer<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'' <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1042 2014-06-15T15:01:32Z

<p>Admin: /* Ph.D. Students */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Julian Kemmerer<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs) <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=People&diff=1041 2014-06-15T15:01:20Z

<p>Admin: /* Ph.D. Students */</p> <hr /> <div>== Faculty ==<br /> [[Baris Taskin]]<br /> <br /> == Ph.D. Students ==<br /> <br /> [[Leo Filippini]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Vasil Pano]]<br /> <br /> [[Karthik Sangaiah]]<br /> <br /> [[Can Sitik]]<br /> <br /> [[Ying Teng]]<br /> <br /> == MS Students ==<br /> <br /> Stephen DeLuca<br /> <br /> Julian Kemmerer<br /> <br /> Andrew Sauber<br /> <br /> == Undergraduate Researchers ==<br /> <br /> Fernando Ellis (2013) [RIT - NSF REU]<br /> <br /> Daniel Schoepflin (2013) [Drexel STARS scholar]<br /> <br /> Giordano Salvador (2013-2014) [Penn - NSF REU]<br /> <br /> [[Vasil Pano]] (2013-2014) [Drexel] <br /> <br /> Andrew Apollonsky (2012) [Cooper Union - NSF REU]<br /> <br /> Michael Miller (2012) [Goshen College - NSF REU]<br /> <br /> Michael Sineriz (2012) [Maryland - NSF REU]<br /> <br /> [[Scott Lerner ]](2012-2014)<br /> <br /> Isuru Daulagala (2012) [Drexel]<br /> <br /> Catherine Leis (2011) [Drexel]<br /> <br /> Asha Habib (2011) [Bryn Mawr College - NSF REU]<br /> <br /> Kevin Linger (2011) [University of Virginia - NSF REU]<br /> <br /> Andrew Richard Benton (2011) [Drexel STARS scholar]<br /> <br /> David Hocky (2011) [Drexel STARS scholar]<br /> <br /> Yusuf Aksehir (2010) [Sabanci University]<br /> <br /> Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at Carnegie Mellon University]<br /> <br /> Michael Edoror (2010) [University of Maryland - NSF REU]<br /> <br /> Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]<br /> <br /> S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]<br /> <br /> Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]<br /> <br /> Danh Nguyen (2007) [Ph.D. at Drexel University]<br /> <br /> *Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu<br /> <br /> == Senior Design Advisees ==<br /> <br /> Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)<br /> <br /> Jeffrey Eckert, Neev Wanvari (2012-2013)<br /> <br /> Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)<br /> <br /> Eric Fargnoli, Colby Weingarten (2009-2010)<br /> <br /> Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)<br /> <br /> Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)<br /> <br /> Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)<br /> <br /> James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)<br /> <br /> Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)<br /> <br /> David Dimm, Roshani Patel (2005-2006)<br /> <br /> == High-School Researchers ==<br /> <br /> Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]<br /> <br /> == Group Alumni ==<br /> <br /> [[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs) <br /> <br /> Swetha George (M.S., 2012) [Ph.D. at the University of Rochester]<br /> <br /> [[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''<br /> <br /> Kevin Daly (MS, 2011) [First job: Washington, DC]<br /> <br /> [[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research]<br /> <br /> Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]<br /> <br /> [[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''<br /> <br /> Yaswanth Simhadri (MS, 2008)<br /> <br /> Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''</div>

Admin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1040 2014-06-15T15:00:47Z

<p>Admin: /* Thesis and Dissertations */</p> <hr /> <div>== Conferences ==<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, to appear in ''IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in ''IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. <br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

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