https://research.coe.drexel.edu/ece/vlsi/api.php?action=feedcontributions&feedformat=atom&user=Can 2026-05-12T23:13:31Z User contributions MediaWiki 1.39.3 https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1472 2016-03-07T07:11:19Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - 2015''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # C. Sitik, W. Liu, B. Taskin and E. Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, (accepted to) ''IEEE Transactions on Very Large Scale Integration Systems (TVLSI)'', January 2016.<br /> # C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # C. Sitik and B. Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> # W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, to appear in ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> #W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # C. Sitik, S. Lerner and B. Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # C. Sitik, L. Filippini, E. Salman and B. Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # C. Sitik, P. Nagvajara and B. Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # C. Sitik and B. Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # C. Sitik and B. Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # C. Sitik and B. Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # C. Sitik and B. Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> Hillsboro, OR 97124 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:cansitik@gmail.com cansitik@gmail.com] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1460 2016-02-29T02:28:35Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - 2015''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # C. Sitik, W. Liu, B. Taskin and E. Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, (accepted to) ''IEEE Transactions on Very Large Scale Integration Systems (TVLSI)'', January 2016.<br /> # C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # C. Sitik and B. Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> # W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, to appear in ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> #W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # C. Sitik, S. Lerner and B. Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # C. Sitik, L. Filippini, E. Salman and B. Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # C. Sitik, P. Nagvajara and B. Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # C. Sitik and B. Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # C. Sitik and B. Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # C. Sitik and B. Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # C. Sitik and B. Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1459 2016-02-29T02:28:13Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - 2015''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # C. Sitik, W. Liu, B. Taskin and E. Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, (accepted to) ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', January 2016.<br /> # C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # C. Sitik and B. Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> # W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, to appear in ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> #W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # C. Sitik, S. Lerner and B. Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # C. Sitik, L. Filippini, E. Salman and B. Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # C. Sitik, P. Nagvajara and B. Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # C. Sitik and B. Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # C. Sitik and B. Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # C. Sitik and B. Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # C. Sitik and B. Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1458 2016-02-29T02:26:32Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - 2015''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # C. Sitik and B. Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> # W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, to appear in ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> #W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # C. Sitik, S. Lerner and B. Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # C. Sitik, L. Filippini, E. Salman and B. Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # C. Sitik, P. Nagvajara and B. Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # C. Sitik and B. Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # C. Sitik and B. Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # C. Sitik and B. Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # C. Sitik and B. Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1362 2015-11-18T22:21:37Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # C. Sitik and B. Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #W. Liu, E. Salman, C. Sitik and B. Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # C. Sitik, S. Lerner and B. Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # C. Sitik, L. Filippini, E. Salman and B. Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # C. Sitik, P. Nagvajara and B. Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # C. Sitik and B. Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # C. Sitik and B. Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # C. Sitik and B. Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # C. Sitik and B. Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1359 2015-11-17T02:55:48Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1358 2015-11-16T20:07:15Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1357 2015-11-16T20:06:32Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, (accepted to) ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', March 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1356 2015-11-16T20:04:58Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, (accepted to) ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', March 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, pp. 13:1--13:20, September 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1355 2015-11-16T20:03:39Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, pp. 13:1--13:20, September 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1339 2015-09-07T05:06:46Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, (to appear) ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp.~1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, (accepted to) ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', March 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, (accepted to) ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', January 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1338 2015-09-02T05:11:24Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Pre- and Post-Si Power and Timing Modeling<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1337 2015-09-02T05:10:45Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Pre- and Post-Si Power and Timing Modeling<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1336 2015-08-24T06:22:59Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1335 2015-08-24T06:21:55Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, (to appear) ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp.~1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, (accepted to) ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', March 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, (accepted to) ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', January 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1334 2015-08-24T06:20:36Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1333 2015-08-24T06:00:19Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1332 2015-08-24T06:00:03Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing<br /> Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=News/Events&diff=1239 2015-04-18T23:00:21Z

<p>Can: </p> <hr /> <div>* Scott Lerner received the DoD NSDEG fellowship (declined) in 2015.<br /> <br /> <br /> * Scott Lerner received the NSF GRFP Fellowship in 2015. [http://drexel.edu/fellowships/studentprofiles/profiles/Scott%20Lerner/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:ScottNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Giordano Salvador received the NSF GRFP Fellowship in 2015. <br /> <br /> <br /> * Can Sitik and Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2015.<br /> <br /> <br /> * Prof. Taskin is the TPC chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2015 [http://sliponline.org]<br /> <br /> <br /> * Scott Lerner received the A. Richard Newton Young Student Fellow Program travel grant from Design Automation Conference in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the NSF GRFP Fellowship in 2014. [http://drexel.edu/fellowships/studentprofiles/profiles/Karthik%20Sangaiah/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:PacoNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Can Sitik received the Leroy L. Rosser fellowship from Drexel University in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2014.<br /> <br /> <br /> * Best paper nomination for Can Sitik at the ACM GLSVLSI 2013 for the paper entitled [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]].<br /> <br /> <br /> * Can Sitik received the George Hill, Jr. fellowship from Drexel University in 2013.<br /> <br /> <br /> * Prof. Taskin is selected the &quot;Young Electrical Engineer of the Year 2013&quot; by the IEEE Philadelphia Section.<br /> <br /> <br /> * Prof. Taskin organized and presented a tutorial on &quot;Resonant Clocking&quot; with Prof. Matthew Guthaus of UCSC and Drexel VLSI Lab Alumni Dr. Vinayak Honkote of Intel at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012 in San Jose, CA. [http://iccad.com/2012_event_details?id=149-10-D program link]<br /> <br /> <br /> * Drexel student newspaper article on hybrid wireless NoC project [http://thetriangle.org/2012/08/31/antennas-allow-microchips-to-go-wireless/ Drexel Triangle link]<br /> * News release from Drexel about our hybrid wireless NoC project [http://www.drexel.edu/now/news-media/releases/archive/2012/August/Wireless-Network-on-Chip/ August 2012 DrexelNOW link] <br /> &lt;gallery&gt;<br /> File:Chip_CourtesyBarisTaskin-300x225.jpg<br /> File:microchip.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Dr. Taskin received the ACM SIGDA Distinguished Service Award in 2012.<br /> <br /> <br /> * Ying Teng received the George Hill, Jr. fellowship from Drexel University in 2012.<br /> <br /> <br /> * See our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> <br /> * Ying Teng received the N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2011.<br /> <br /> <br /> * Here is the report for the Drexel Office of International Programs travel award for Dr. Taskin to ISCAS'11. [http://www.drexel.edu/international/assets/pdf/ita/faculty/2011-Taskin_Baris.pdf]<br /> &lt;gallery&gt;<br /> File:Facultyspotlight.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ying Teng's first journal paper &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot; is featured on the cover of the Journal of Low Power Electronics (JOLPE) in December 2010. Check out the [[Publications]] page for details.<br /> &lt;gallery&gt;<br /> File:JOLPEDec10.jpg<br /> File:jlp64Fig.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ankit More received the George Hill, Jr. fellowship from Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Ying Teng presented their work in University Booth, at the ACM/IEEE Design Automation Conference in Anaheim, CA, in 2010.<br /> &lt;gallery&gt;<br /> File:Jianchao_2010_dac.JPG<br /> File:Ying_2010_dac.JPG<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Sharat Chandra recipient of the Young Student Support Program Award for the Design Automation Conference in Anaheim, CA in 2010:<br /> [http://www.sigda.org/youngstudent.html Young Student Support Program DAC]<br /> <br /> <br /> * The NSF-funded REU Site opportunity on &quot;Computing for Power and Energy&quot; directed by Dr. Taskin is starting in Summer 2010: [http://reu.ece.drexel.edu REU Site on Computing for Power and Energy: The Old, The New and The Renewable]. This site will run for the next three years.<br /> &lt;gallery&gt;<br /> File:DrexelREU2010web.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Vinayak received the first N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote presented their work in University Booth and Ph.D. Forum, respectively, at the ACM/IEEE Design Automation Conference in San Francisco, CA, in 2009.<br /> &lt;gallery&gt;<br /> File:dac2009_jianchao.jpg<br /> File:dac2009_vinayak.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote participated in the SIGDA CADAthlon at ICCAD 2008 in San Jose, CA.<br /> &lt;gallery&gt;<br /> File:cadathlon080.jpg<br /> File:cadathlon081.jpg<br /> File:cadathlon082.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Accepting the ''A. Richard Newton Award'' at the ACM/IEEE Design Automation Conference in 2007.<br /> &lt;gallery&gt;<br /> File:dac2007.jpg<br /> File:dac20071.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Drexel Senior Design team, also winners of the CE award, presented at the University Booth at the ACM/IEEE Design Automation Conference in San Diego, CA, in 2007.<br /> &lt;gallery&gt;<br /> File:senior07.jpg<br /> File:senior071.jpg<br /> File:senior072.jpg<br /> &lt;/gallery&gt;</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1161 2015-02-18T16:12:49Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Can_CV.pdf&diff=1160 2015-02-18T16:11:38Z

<p>Can: uploaded a new version of &quot;File:Can CV.pdf&quot;</p> <hr /> <div></div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1159 2015-02-18T05:56:57Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1158 2015-02-12T18:06:07Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, to appear in the ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> #Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Gio Salvador, Baris Taskin, Mark Hempstead, ”SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, to appear in ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, to appear in ''IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, to appear in ''IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. <br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1156 2015-01-10T02:15:34Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1155 2015-01-09T20:58:00Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C671: EDA for VLSI I (Winter 2015)<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1154 2015-01-09T20:56:41Z

<p>Can: </p> <hr /> <div>=Winter 2015=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || ||align=&quot;center&quot;| Meeting (Scott) || ||<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || CEG Symposia || || ECE-C671 Office Hour || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || CEG Symposia || || ECE-C671 Office Hour || || ECE-C671 Class<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting (SRC) || ||align=&quot;center&quot;| Meeting (George) || || ECE-C671 Class<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting (SRC) || || || || ECE-C671 Class<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1153 2015-01-09T20:54:02Z

<p>Can: </p> <hr /> <div>=Winter 2015=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || ||align=&quot;center&quot;| Meeting (Scott) || ||<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || CEG Symposia || || ECE-C671 Office Hour || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || CEG Symposia || || ECE-C671 Office Hour || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting (SRC) || ||align=&quot;center&quot;| Meeting (George) || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting (SRC) || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1152 2015-01-09T20:53:29Z

<p>Can: </p> <hr /> <div>=Winter 2015=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || || Meeting (Scott) || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || CEG Symposia || || ECE-C671 Office Hour || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || CEG Symposia || || ECE-C671 Office Hour || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting (SRC) || || Meeting (George) || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting (SRC) || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1151 2015-01-09T20:52:42Z

<p>Can: </p> <hr /> <div>=Winter 2015=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || || || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || CEG Symposia || || || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || CEG Symposia || || Meeting (George) || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting (SRC) || || || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting (SRC) || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1150 2015-01-09T20:04:01Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1149 2015-01-09T20:02:54Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1148 2015-01-09T20:01:52Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> #Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Gio Salvador, Baris Taskin, Mark Hempstead, ”SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, to appear in Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), 29-31 March 2015.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, to appear in ''IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, to appear in ''IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. <br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1147 2015-01-09T20:01:34Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Weicheng Liu, Emre Salman, Can Sitik, and Baris Taskin, “Enhanced Level Shifter for Multi-Voltage Operation,” to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015.<br /> #Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Gio Salvador, Baris Taskin, Mark Hempstead, ”SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, to appear in Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), 29-31 March 2015.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, to appear in ''IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, to appear in ''IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. <br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1113 2014-10-30T15:30:19Z

<p>Can: </p> <hr /> <div>=Fall 2014=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || ||align=&quot;center&quot;| Meeting (Sneha) || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || CEG Symposia || || || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || CEG Symposia || || Meeting (George) || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting (SRC) || || || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting (SRC) || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1112 2014-10-30T15:29:57Z

<p>Can: </p> <hr /> <div>=Fall 2014=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || ||align=&quot;center&quot;| Meeting (Sneha) || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || CEGS || || || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || CEGS || || Meeting (George) || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting (SRC) || || || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting (SRC) || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1109 2014-10-02T14:58:39Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1108 2014-09-25T22:15:59Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1107 2014-09-25T20:40:19Z

<p>Can: </p> <hr /> <div>=Fall 2014=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || ||align=&quot;center&quot;| Meeting || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || || Meeting<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1106 2014-09-25T17:42:36Z

<p>Can: </p> <hr /> <div>=Fall 2014=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || ||align=&quot;center&quot;| Meeting || ||<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1105 2014-09-25T17:42:03Z

<p>Can: </p> <hr /> <div>=Fall 2014=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || || Meeting ||align=&quot;center&quot;| ||<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Weekly_Schedule&diff=1104 2014-09-25T17:41:06Z

<p>Can: </p> <hr /> <div>=Fall 2014=<br /> <br /> {| border=&quot;1&quot; cellpadding=&quot;10&quot;<br /> |align=&quot;center&quot;| ||align=&quot;center&quot;| Monday ||align=&quot;center&quot;| Tuesday ||align=&quot;center&quot;| Wednesday ||align=&quot;center&quot;| Thursday ||align=&quot;center&quot;| Friday<br /> |-<br /> |align=&quot;center&quot;| 09.00-10.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 10.00-11.00(AM) || || || Meeting || ||<br /> |-<br /> |align=&quot;center&quot;| 11.00-12.00(AM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 12.00-1.00(PM) || || || || ||<br /> |-<br /> |align=&quot;center&quot;| 1.00-2.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 2.00-3.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 3.00-4.00(PM) || Meeting || || || ||<br /> |-<br /> |align=&quot;center&quot;| 4.00-5.00(PM) || Meeting || || || ||<br /> |}</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1101 2014-09-24T20:46:29Z

<p>Can: </p> <hr /> <div>== Conferences ==<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, to appear in ''IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in ''IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. <br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''High Performance IC Clock Networks with Mesh and Tree Topologies'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits'', 2007</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1100 2014-09-24T20:45:14Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ====Conferences====<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1099 2014-09-23T21:13:42Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> ===Journals===<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> ===Conferences===<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1098 2014-09-23T21:12:44Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> <br /> =Journals=<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yun and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, (accepted to) ''ACM Journal of Emerging Technologies in Computing (JETC) Systems'', September 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> <br /> =Conferences=<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1071 2014-08-28T03:34:59Z

<p>Can: </p> <hr /> <div>[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1070 2014-08-28T03:33:19Z

<p>Can: </p> <hr /> <div>[[File:Profilepic.jpg|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1069 2014-08-28T03:32:43Z

<p>Can: </p> <hr /> <div>[[File:Profilepic.jpg|right|border|frame|[[Can Sitik]]|5px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1068 2014-08-28T03:32:27Z

<p>Can: </p> <hr /> <div>[[File:Profilepic.jpg|right|border|frame|[[Can Sitik]]|25px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&diff=1067 2014-08-28T03:32:11Z

<p>Can: </p> <hr /> <div>[[File:Profilepic.jpg|right|border|frame|[[Can Sitik]]|15px]]<br /> <br /> ==Education==<br /> '''Ph.D. in Computer Engineering, 2011 - Present''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''M.S. in Computer Engineering, 2013''' &lt;br&gt; <br /> :Drexel University, Philadelphia, Pennsylvania, USA<br /> <br /> '''B.S. in [http://www.eee.metu.edu.tr Electrical and Electronics Engineering], 2011 ''' &lt;br&gt;<br /> :[http://metu.edu.tr Middle East Technical University(METU)], Ankara, Turkey<br /> <br /> ==Research Interests==<br /> * Low Swing Clock Tree Synthesis<br /> * Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]<br /> * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]<br /> * Clock Network Design with FinFETs<br /> * Physical Design of System-on-Chips<br /> <br /> ==Curriculum Vitae==<br /> [[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]<br /> <br /> ==Publications==<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, to appear in the ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014.<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, to appear in the ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> [http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&amp;hl=en '''Google Scholar Page''']<br /> <br /> ==Teaching==<br /> * ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)<br /> * ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)<br /> * ENGR-231: Linear Engineering Systems (Spring, Fall 2012)<br /> * ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)<br /> :Please refer to my [[Weekly Schedule]] to ask for an appointment<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Department of ECE &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> Bossone 324 &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] &lt;br&gt;<br /> <br /> '''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&amp;trk=hb_tab_pro_top A. Can Sitik]</div>

Can