[[File:JianchaoSmall.jpg|right|border|frame|[[Jianchao Lu]]|25px]]

==Education==
'''Ph.D. in Computer Engineering, 2007-Present''' 
:Drexel University, Philadelphia, Pennsylvania, USA

'''M.S. in Computer Engineering, 2009''' 
:Drexel University, Philadelphia, Pennsylvania, USA

'''B.S. in Electronics and Information Engineering, 2007''' 
:Zhejiang University, Hangzhou, China.

==Research Interests==
* Clock Network Synthesis including Clock Tree/Mesh Synthesis and Resonant Clocking
* Physical Design Methodologies in general including Floorplanning, Placement and Routing
* Power and Timing Optimization
* Static and Statistical Timing analysis
* Parallel Computing

==Curriculum Vitae==
[http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/5/51/Jlu_cv_v2.pdf Jianchao Lu CV (Nov 2010)]

== Selected Publications ==
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", to appear in the ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011.
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", to appear in the ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011.
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011.
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", to appear in the ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011.
# Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, "Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings", to appear in the ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp.232--236.
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 324 
Philadelphia 
Pennsylvania 19104 

'''Phone:''' (215) 301-8795 
'''Fax:''' (215) 895-1695 
'''Email: '''jl597@drexel.edu