https://research.coe.drexel.edu/ece/vlsi/api.php?action=feedcontributions&feedformat=atom&user=Leo 2026-05-14T10:21:58Z User contributions MediaWiki 1.39.3 https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_Filippini_CV.pdf&diff=4056 2019-02-05T22:44:45Z

<p>Leo: Leo uploaded a new version of File:Leo Filippini CV.pdf</p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_ISCAS18.pdf&diff=4021 2019-01-28T21:12:58Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_MWSCAS17.pdf&diff=4016 2019-01-28T21:12:29Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_ISQED17.pdf&diff=4011 2019-01-28T21:11:33Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_ISCAS16.pdf&diff=4006 2019-01-28T21:10:30Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_ICCD15.pdf&diff=4001 2019-01-28T21:08:32Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3996 2019-01-28T21:07:49Z

<p>Leo: </p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II. - [[Media:Leo_TCAS2_draft.pdf | Draft]]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [[Media:Leo_ISCAS18.pdf | Draft]]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017. [[Media:Leo_MWSCAS17.pdf | Draft]]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot; ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017. [[Media:Leo_ISQED17.pdf | Draft]]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016. [[Media:Leo_ISCAS16.pdf | Draft]]<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic,&quot; &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [[Media:Leo_ICCD15.pdf | Draft]]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_ICCD16.pdf&diff=3991 2019-01-28T21:06:59Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3986 2019-01-28T21:05:44Z

<p>Leo: </p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II. - [[Media:Leo_TCAS2_draft.pdf | Draft]]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [[Media:Leo_ISCAS18.pdf | Draft]]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017. [[Media:Leo_MWSCAS17.pdf | Draft]]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot; ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017. [[Media:Leo_ISQED17.pdf | Draft]]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016. [[Media:Leo_ISCAS16.pdf | Draft]]<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic,&quot; &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [[Media:Leo_ICCD16.pdf | Draft]]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3981 2019-01-28T21:01:39Z

<p>Leo: </p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II. - [[Media:Leo_TCAS2_draft.pdf | Draft]]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot; ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017. [https://doi.org/10.1109/ISQED.2017.7918339 link]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3976 2019-01-28T20:58:02Z

<p>Leo: /* Journals */</p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II. - [[Media:Leo_TCAS2_draft.pdf | Draft]]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_TCAS2_draft.pdf&diff=3971 2019-01-28T20:22:31Z

<p>Leo: Leo uploaded a new version of File:Leo TCAS2 draft.pdf</p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3931 2019-01-22T18:33:21Z

<p>Leo: </p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II. [[Media:Leo_TCAS2_draft.pdf | draft]]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=3926 2019-01-22T18:32:54Z

<p>Leo: /* Journals */</p> <hr /> <div>== Conferences ==<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018.<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, “NoC Router Lifetime Improvement using Per-Port Router Utilization,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508.<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193.<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II. [[Media:Leo_TCAS2_draft.pdf | draft]]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)&quot;, accepted January 2019<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', (in print) accepted November 2018, Digital Object Identifier: 10.1109/TVLSI.2018.2888958.<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', (in print) accepted October 2018.<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019.<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs,&quot; ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018.<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018.<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_Filippini_CV.pdf&diff=3921 2019-01-22T18:31:25Z

<p>Leo: Leo uploaded a new version of File:Leo Filippini CV.pdf</p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3916 2019-01-22T18:30:07Z

<p>Leo: </p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II, Oct. 2018. [[Media:Leo_TCAS2_draft.pdf | draft]]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_TCAS2_draft.pdf&diff=3911 2019-01-22T18:29:27Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3906 2019-01-22T17:42:35Z

<p>Leo: /* Journals */</p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II, Oct. 2018.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3901 2019-01-22T17:37:25Z

<p>Leo: </p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (accepted) IEEE Transactions on Circuits and Systems II, Oct. 2018. [[Media:Leo_TCAS2_draft.pdf | draft]]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_Filippini_CV.pdf&diff=3596 2018-11-01T14:47:24Z

<p>Leo: Leo uploaded a new version of File:Leo Filippini CV.pdf</p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3591 2018-11-01T14:40:00Z

<p>Leo: /* Research Interests */</p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recovery Logic<br /> * Low-power Data Converters<br /> * Logic Synthesis<br /> * Automatic Layout Generation<br /> * Low-swing Flip Flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (under review) IEEE Transactions on Circuits and Systems II, Oct. 2018.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3586 2018-11-01T14:03:29Z

<p>Leo: /* Journals */</p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # L. Filippini and B. Taskin, “123: A Tool For Charge Recovery Logic Synthesis,” (in preparation) IEEE Transactions on VLSI Systems.<br /> # L. Filippini and B. Taskin, “The adiabatically driven strongarm comparator,” (under review) IEEE Transactions on Circuits and Systems II, Oct. 2018.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> <br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3581 2018-11-01T14:00:48Z

<p>Leo: </p> <hr /> <div>[[File:Leo.jpg|300px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo.jpg&diff=3576 2018-11-01T14:00:15Z

<p>Leo: Leo uploaded a new version of File:Leo.jpg</p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo.jpg&diff=3571 2018-11-01T13:56:01Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3566 2018-11-01T13:55:29Z

<p>Leo: </p> <hr /> <div>[[File:Leo.JPG|200px|thumb|right|Leo Filippini]]<br /> <br /> ==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3481 2018-08-11T04:45:46Z

<p>Leo: /* Publications */</p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results,&quot; in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', pp. 1505--1508, Aug. 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3476 2018-08-11T04:44:12Z

<p>Leo: /* Curriculum Vitae */</p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini CV]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, (to appear) ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=3471 2018-08-11T04:43:48Z

<p>Leo: CV</p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Curriculum Vitae==<br /> [[Media:Leo_Filippini_CV.pdf | Leo Filippini January 2018]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, (to appear) ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo_Filippini_CV.pdf&diff=3466 2018-08-11T04:42:48Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=2656 2018-01-24T19:51:32Z

<p>Leo: /* Résumé */</p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Résumé==<br /> [[Media:Leo-Filippini-CV-Jan2018.pdf | Leo Filippini January 2018]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, (to appear) ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo-Filippini-CV-Jan2018.pdf&diff=2651 2018-01-24T19:51:02Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=2566 2018-01-24T16:09:30Z

<p>Leo: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” (to appear) in &quot;Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)&quot;, May 2018.<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, “Charge Recovery Implementation of an Analog Comparator: Initial Results,” in Proc. IEEE 60th Int. Midwest Symp. Circuits and Systems (MWSCAS), pp. 1505–1508, Aug. 2017.<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193.<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=2386 2017-10-20T17:00:44Z

<p>Leo: </p> <hr /> <div>== Conferences ==<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, “Charge Recovery Implementation of an Analog Comparator: Initial Results,” in Proc. IEEE 60th Int. Midwest Symp. Circuits and Systems (MWSCAS), pp. 1505–1508, Aug. 2017.<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193.<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=2381 2017-10-20T17:00:31Z

<p>Leo: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin,“Charge Recovery Implementation of an Analog Comparator: Initial Results,” in Proc. IEEE 60th Int. Midwest Symp. Circuits and Systems (MWSCAS), pp. 1505–1508, Aug. 2017.<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193.<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=2291 2017-10-06T19:54:17Z

<p>Leo: </p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Résumé==<br /> [[Media:Leo-Filippini-CV-Oct2017.pdf | Leo Filippini October 2017]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, (to appear) ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=2286 2017-10-06T19:53:47Z

<p>Leo: </p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Résumé==<br /> [[Media:Leo-Filippini-CV-Oct2017.pdf | Leo Filippini October 2017]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, (to appear) ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=2281 2017-10-06T19:52:47Z

<p>Leo: /* Résumé */</p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Résumé==<br /> [[Media:Leo-Filippini-CV-Oct2017.pdf | Leo Filippini October 2017]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo-Filippini-CV-Oct2017.pdf&diff=2276 2017-10-06T19:52:20Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=2056 2017-07-06T14:44:05Z

<p>Leo: </p> <hr /> <div>== Conferences ==<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, (to appear) ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2017.<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, (to appear) ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017.<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, (to appear) ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, (to appear) ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=2051 2017-07-06T14:38:53Z

<p>Leo: </p> <hr /> <div>== Conferences ==<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, (to appear) ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2017.<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, (to appear) ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017.<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, (to appear) ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017.<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, (to appear) ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, (to appear) ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1941 2017-05-09T15:56:24Z

<p>Leo: </p> <hr /> <div>== Conferences ==<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, (to appear) ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017.<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, (to appear) ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017.<br /> # Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, (to appear) ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, (to appear) ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, (to appear) ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017.<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=1741 2017-02-02T22:03:28Z

<p>Leo: /* Résumé */</p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Résumé==<br /> [[Media:Leo-Filippini-CV-Feb2017.pdf | Leo Filippini Feb 2017]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo-Filippini-CV-Feb2017.pdf&diff=1736 2017-02-02T22:02:56Z

<p>Leo: </p> <hr /> <div></div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=1731 2017-02-02T21:56:39Z

<p>Leo: </p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Résumé==<br /> [[Media:Leo-Filippini-resume.pdf | Leo Filippini April 2016]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1631 2016-12-06T19:10:21Z

<p>Leo: </p> <hr /> <div>== Conferences ==<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;. (to appear) ''International Symposium on Quality Electronic Design (ISQED)'', March 2017<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1626 2016-12-06T19:09:45Z

<p>Leo: </p> <hr /> <div>== Conferences ==<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;. (to appear) &quot;International Symposium on Quality Electronic Design (ISQED)&quot;, March 2017<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=1621 2016-12-06T19:08:42Z

<p>Leo: </p> <hr /> <div>== Conferences ==<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;. (to appear) &quot;International Symposium on Quality Electronic Design (ISQED)&quot;, March 2017<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic,&quot; (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication,&quot; (to appear) ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance,&quot; ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. <br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9.<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|&quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.<br /> # Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.<br /> # Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|&quot;Multi-Voltage Domain Clock Mesh Design&quot;]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.<br /> # Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|&quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.<br /> # Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|&quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.<br /> # Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|&quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.<br /> # Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|&quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.<br /> # Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|&quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.<br /> # Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|&quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.<br /> # Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|&quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.<br /> # Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|&quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.<br /> <br /> == Journals ==<br /> <br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks,&quot; ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. <br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. <br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. <br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=Leo_Filippini&diff=1488 2016-04-27T18:20:46Z

<p>Leo: </p> <hr /> <div>==Education==<br /> '''Ph.D. in Electronic Engineering, ongoing''' &lt;br&gt; <br /> :Drexel University, Philadelphia, PA, USA<br /> <br /> '''M.S. in Electronic Engineering, 2013''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> '''B.S. in Information Engineering, 2010''' &lt;br&gt; <br /> :University of Brescia, Brescia, Italy<br /> <br /> ==Research Interests==<br /> * Adiabatic and Charge Recycling logic<br /> * Low-swing flip flops<br /> <br /> ==Résumé==<br /> [[Media:Leo-Filippini-resume.pdf | Leo Filippini April 2016]]<br /> <br /> ==Publications==<br /> <br /> ====Journals====<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', August 2015 [http://dx.doi.org/10.1145/2701617 link].<br /> ====Conferences====<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications,” (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.<br /> # Leo Filippini, Emre Salman and Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, &quot;IEEE International Conference on Computer Design&quot; (ICCD), October 2015. [http://dx.doi.org/10.1109/ICCD.2015.7357158 link]<br /> # Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014. [http://dx.doi.org/10.1109/ISVLSI.2014.53 link]<br /> <br /> ==Contact Information==<br /> '''Address:''' &lt;br&gt;<br /> 3141 Chestnut Street &lt;br&gt;<br /> Drexel University &lt;br&gt;<br /> ECE Department &lt;br&gt;<br /> Philadelphia, PA 19104 &lt;br&gt;<br /> <br /> '''Office:''' Bossone 324 &lt;br&gt;<br /> '''Email:''' [mailto:lf458@drexel.edu lf458@drexel.edu] &lt;br&gt;</div>

Leo https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Leo-Filippini-resume.pdf&diff=1487 2016-04-27T18:19:25Z

<p>Leo: </p> <hr /> <div></div>

Leo