[[File:MikeLui.jpg|200px|thumb|right|Mike Lui]]

==Education==
'''Ph.D. in Computer Engineering, 2014 - Present''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

'''B.S. and M.S. in Computer Engineering, 2012 ''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

==Research Interests==
* Workload Profiling Techniques
* Hardware-Software Co-Design
* Heterogeneous Computer Architecture
* Low-power Embedded Systems and Internet-of-Things devices

==Academic Interests==
* Education
* Fonts, formatting, and data visualization
* Human-Computer Interaction
* 3D Graphics

==Resume==
[[media:Michael_Lui_CV.pdf|Michael Lui CV (2020)]]

==Publications==
#M. Lui, K. Sangaiah, M. Hempstead, and B. Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, Northern Ireland, April 2018.
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ACM Transactions on Architecture and Code Optimization (TACO), April 2018.
#V. Pano, S. Lerner, I. Yilmaz, M. Lui, and B. Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.
#A. Hankin, T. Shapira, K. Sangaiah, M. Lui, and M. Hempstead, "Evaluation of Non-Volatile Memory based Last Level Cache given Modern Use Case Behavior", IEEE International Symposium on Workload Characterization (IISWC), Orlando, Florida, November 2019.

==Tutorials==
* SIGIL - workload analysis tools and techniques for hardware-software co-design
** 2016, IEEE International Symposium on Workload Characterization (IISWC '16), Providence, RI
** 2015, IEEE International Conference on Computer Design (ICCD '15), New York, NY
** 2015, IEEE International Symposium on Workload Characterization (IISWC '15), Atlanta, GA
** 2015, IEEE Symposium on High Performance Computer Architecture (HPCA '15), San Francisco, CA

==Posters==
* Simplifying Workload Analysis
** 2017, ARM Research Summit, Cambridge, UK

==Teaching==
* 2018-2019 Academic Year
** TA ECEC-201: Advanced Programming for Engineers (Intro to C)
** TA ECE-105: Programming for Engineers II (Scientific Computing with Python)
* 2017-2018 Academic Year
** TA ECE-200: Digital Logic Design
* 2016-2017 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-302: Digital Systems Projects
** TA ECEC-355: Computer Architecture
** TA ECEC-357: Introduction to Computer Networks
* 2015-2016 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-356: Embedded Systems
** TA ECEC-355: Computer Architecture
** TA ECEL-304: ECE Lab 4
* 2014-2015 Academic Year
** TA ENGR-201: Evaluation and Presentation of Experimental Data I
** TA ENGR-231: Linear Engineering Systems
** TA ENGR-202: Evaluation and Presentation of Experimental Data II
** TA ENGR-232: Dynamic Engineering Equations


==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 405 
Philadelphia, PA 19104 

'''Email:''' [mailto:mikelui@drexel.edu mikelui@drexel.edu]

'''Drexel:''' [http://drexel.edu/ece/contact/adjunct-faculty/Michael%20Lui/ drexel.edu]

'''Linkedin:''' [https://www.linkedin.com/in/mikelui/ in/mikelui]

'''GitHub:''' [https://github.com/mikelui git.io/mikelui]

'''Website:''' [http://mikelui.io mikelui.io]

File:Michael Lui CV.pdf

2020-02-02T18:01:28Z

Mdl45: Mdl45 uploaded a new version of File:Michael Lui CV.pdf

Michael Lui

2019-11-06T22:29:44Z

Mdl45: /* Publications */

[[File:MikeLui.jpg|200px|thumb|right|Mike Lui]]

==Education==
'''Ph.D. in Computer Engineering, 2014 - Present''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

'''B.S. and M.S. in Computer Engineering, 2012 ''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

==Research Interests==
* Workload Profiling Techniques
* Hardware-Software Co-Design
* Heterogeneous Computer Architecture
* Low-power Embedded Systems and Internet-of-Things devices

==Academic Interests==
* Education
* Fonts, formatting, and data visualization
* Human-Computer Interaction
* 3D Graphics

==Resume==
[[media:Michael_Lui_CV.pdf|Michael Lui CV (2019)]]

==Publications==
#M. Lui, K. Sangaiah, M. Hempstead, and B. Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, Northern Ireland, April 2018.
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ACM Transactions on Architecture and Code Optimization (TACO), April 2018.
#V. Pano, S. Lerner, I. Yilmaz, M. Lui, and B. Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.
#A. Hankin, T. Shapira, K. Sangaiah, M. Lui, and M. Hempstead, "Evaluation of Non-Volatile Memory based Last Level Cache given Modern Use Case Behavior", IEEE International Symposium on Workload Characterization (IISWC), Orlando, Florida, November 2019.

==Tutorials==
* SIGIL - workload analysis tools and techniques for hardware-software co-design
** 2016, IEEE International Symposium on Workload Characterization (IISWC '16), Providence, RI
** 2015, IEEE International Conference on Computer Design (ICCD '15), New York, NY
** 2015, IEEE International Symposium on Workload Characterization (IISWC '15), Atlanta, GA
** 2015, IEEE Symposium on High Performance Computer Architecture (HPCA '15), San Francisco, CA

==Posters==
* Simplifying Workload Analysis
** 2017, ARM Research Summit, Cambridge, UK

==Teaching==
* 2018-2019 Academic Year
** TA ECEC-201: Advanced Programming for Engineers (Intro to C)
** TA ECE-105: Programming for Engineers II (Scientific Computing with Python)
* 2017-2018 Academic Year
** TA ECE-200: Digital Logic Design
* 2016-2017 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-302: Digital Systems Projects
** TA ECEC-355: Computer Architecture
** TA ECEC-357: Introduction to Computer Networks
* 2015-2016 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-356: Embedded Systems
** TA ECEC-355: Computer Architecture
** TA ECEL-304: ECE Lab 4
* 2014-2015 Academic Year
** TA ENGR-201: Evaluation and Presentation of Experimental Data I
** TA ENGR-231: Linear Engineering Systems
** TA ENGR-202: Evaluation and Presentation of Experimental Data II
** TA ENGR-232: Dynamic Engineering Equations


==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 405 
Philadelphia, PA 19104 

'''Email:''' [mailto:mikelui@drexel.edu mikelui@drexel.edu]

'''Drexel:''' [http://drexel.edu/ece/contact/adjunct-faculty/Michael%20Lui/ drexel.edu]

'''Linkedin:''' [https://www.linkedin.com/in/mikelui/ in/mikelui]

'''GitHub:''' [https://github.com/mikelui git.io/mikelui]

'''Website:''' [http://mikelui.io mikelui.io]

Michael Lui

2019-11-06T22:28:45Z

Mdl45: /* Publications */

[[File:MikeLui.jpg|200px|thumb|right|Mike Lui]]

==Education==
'''Ph.D. in Computer Engineering, 2014 - Present''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

'''B.S. and M.S. in Computer Engineering, 2012 ''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

==Research Interests==
* Workload Profiling Techniques
* Hardware-Software Co-Design
* Heterogeneous Computer Architecture
* Low-power Embedded Systems and Internet-of-Things devices

==Academic Interests==
* Education
* Fonts, formatting, and data visualization
* Human-Computer Interaction
* 3D Graphics

==Resume==
[[media:Michael_Lui_CV.pdf|Michael Lui CV (2019)]]

==Publications==
#M. Lui, K. Sangaiah, M. Hempstead, and B. Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, Northern Ireland, April 2018.
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ACM Transactions on Architecture and Code Optimization (TACO), In Progress.
#V. Pano, S. Lerner, I. Yilmaz, M. Lui, and B. Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018

==Tutorials==
* SIGIL - workload analysis tools and techniques for hardware-software co-design
** 2016, IEEE International Symposium on Workload Characterization (IISWC '16), Providence, RI
** 2015, IEEE International Conference on Computer Design (ICCD '15), New York, NY
** 2015, IEEE International Symposium on Workload Characterization (IISWC '15), Atlanta, GA
** 2015, IEEE Symposium on High Performance Computer Architecture (HPCA '15), San Francisco, CA

==Posters==
* Simplifying Workload Analysis
** 2017, ARM Research Summit, Cambridge, UK

==Teaching==
* 2018-2019 Academic Year
** TA ECEC-201: Advanced Programming for Engineers (Intro to C)
** TA ECE-105: Programming for Engineers II (Scientific Computing with Python)
* 2017-2018 Academic Year
** TA ECE-200: Digital Logic Design
* 2016-2017 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-302: Digital Systems Projects
** TA ECEC-355: Computer Architecture
** TA ECEC-357: Introduction to Computer Networks
* 2015-2016 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-356: Embedded Systems
** TA ECEC-355: Computer Architecture
** TA ECEL-304: ECE Lab 4
* 2014-2015 Academic Year
** TA ENGR-201: Evaluation and Presentation of Experimental Data I
** TA ENGR-231: Linear Engineering Systems
** TA ENGR-202: Evaluation and Presentation of Experimental Data II
** TA ENGR-232: Dynamic Engineering Equations


==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 405 
Philadelphia, PA 19104 

'''Email:''' [mailto:mikelui@drexel.edu mikelui@drexel.edu]

'''Drexel:''' [http://drexel.edu/ece/contact/adjunct-faculty/Michael%20Lui/ drexel.edu]

'''Linkedin:''' [https://www.linkedin.com/in/mikelui/ in/mikelui]

'''GitHub:''' [https://github.com/mikelui git.io/mikelui]

'''Website:''' [http://mikelui.io mikelui.io]

Michael Lui

2019-11-06T22:28:19Z

Mdl45: /* Publications */

[[File:MikeLui.jpg|200px|thumb|right|Mike Lui]]

==Education==
'''Ph.D. in Computer Engineering, 2014 - Present''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

'''B.S. and M.S. in Computer Engineering, 2012 ''' 
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania

==Research Interests==
* Workload Profiling Techniques
* Hardware-Software Co-Design
* Heterogeneous Computer Architecture
* Low-power Embedded Systems and Internet-of-Things devices

==Academic Interests==
* Education
* Fonts, formatting, and data visualization
* Human-Computer Interaction
* 3D Graphics

==Resume==
[[media:Michael_Lui_CV.pdf|Michael Lui CV (2019)]]

==Publications==
#M. Lui, K. Sangaiah, M. Hempstead, and B. Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, Northern Ireland, April 2018.
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ACM Transactions on Architecture and Code Optimization (TACO), April 2018.
#V. Pano, S. Lerner, I. Yilmaz, M. Lui, and B. Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.
#A. Hankin, T. Shapira, K. Sangaiah, M. Lui, and M. Hempstead, "Evaluation of Non-Volatile Memory based Last Level Cache given Modern Use Case Behavior", IEEE International Symposium on Workload Characterization (IISWC), Orlando, Florida, November 2019.

==Tutorials==
* SIGIL - workload analysis tools and techniques for hardware-software co-design
** 2016, IEEE International Symposium on Workload Characterization (IISWC '16), Providence, RI
** 2015, IEEE International Conference on Computer Design (ICCD '15), New York, NY
** 2015, IEEE International Symposium on Workload Characterization (IISWC '15), Atlanta, GA
** 2015, IEEE Symposium on High Performance Computer Architecture (HPCA '15), San Francisco, CA

==Posters==
* Simplifying Workload Analysis
** 2017, ARM Research Summit, Cambridge, UK

==Teaching==
* 2018-2019 Academic Year
** TA ECEC-201: Advanced Programming for Engineers (Intro to C)
** TA ECE-105: Programming for Engineers II (Scientific Computing with Python)
* 2017-2018 Academic Year
** TA ECE-200: Digital Logic Design
* 2016-2017 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-302: Digital Systems Projects
** TA ECEC-355: Computer Architecture
** TA ECEC-357: Introduction to Computer Networks
* 2015-2016 Academic Year
** Instructor ECEC-353: Systems Programming
** TA ECEC-356: Embedded Systems
** TA ECEC-355: Computer Architecture
** TA ECEL-304: ECE Lab 4
* 2014-2015 Academic Year
** TA ENGR-201: Evaluation and Presentation of Experimental Data I
** TA ENGR-231: Linear Engineering Systems
** TA ENGR-202: Evaluation and Presentation of Experimental Data II
** TA ENGR-232: Dynamic Engineering Equations


==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 405 
Philadelphia, PA 19104 

'''Email:''' [mailto:mikelui@drexel.edu mikelui@drexel.edu]

'''Drexel:''' [http://drexel.edu/ece/contact/adjunct-faculty/Michael%20Lui/ drexel.edu]

'''Linkedin:''' [https://www.linkedin.com/in/mikelui/ in/mikelui]

'''GitHub:''' [https://github.com/mikelui git.io/mikelui]

'''Website:''' [http://mikelui.io mikelui.io]

File:ST Capture Replay.png

2019-08-12T16:45:45Z

Mdl45: Mdl45 uploaded a new version of File:ST Capture Replay.png

SynchroTrace

2019-08-12T16:30:33Z

Mdl45: /* Replay Model: */

== SynchroTrace ==

SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of CMPs. The first step, capturing synchronization-aware traces of multi-threaded applications, leverages an extension of prior work (Sigil). The second step represents an timing model for replaying the synchronization-aware traces into external architecture models. Together, these two stages represent ‘SynchroTrace’.

To leverage this methodology for design space exploration, we have developed a prototype of SynchroTrace integrated into the cache and NoC simulators of Gem5 (Ruby and Garnet, respectively). We defined this prototype integration as the SynchroTrace Simulation Framework, and the code for this framework is available below.

=Overview:=

The capture tool is built from Sigil, which leverages the Valgrind dynamic binary instrumentation tool. The processed instructions from the native multi-threaded applications are abstracted into (3) events: Computation (Work performed local to a thread), Communication (Read/Write dependencies between threads), and Synchronization (embedded pthread calls for each thread). These events form a trace for each individual thread, so that these threads may progress in parallel when replaying the traces.

Computation Event (indicated by the $ and * symbols):
[Thread ID, Event Number, Number of Integer Operations, Number of Floating Point Operations, Number of Memory Reads, Number of Memory Writes $ Range of Unique Addresses Written * Range of Unique Addresses Read]

Communication Event (indicated by the # symbol):
[Thread ID, Event Number # Producer Thread ID, Produce Event Number, Range of Unique Addresses Read]

Synchronization Event (indicated by the pth_th and ^ symbol):
[Thread ID, Event Number, pth_ty: Pthread Call Type ^ Address of Synchronization Structure]

=Replay Model:=

Traces are fed into the replay timing model, which acts as an interface into the external architecture models.

[[File:ST_Capture_Replay.png| SynchroTrace Capture/Replay Flow]]

The Replay portion of SynchroTrace is comprised of 4 entities:

Trace Translator – Converts the traces into an event form to be fed into the timing model.

Event Queue Manager – Centralized event queue that manages the timing of thread progression based on the three types of events. The Event Queue Manager also handles the timing for when to send memory requests to the external cache simulator.

Thread Scheduler – Creates and maintains the thread state. The Thread Scheduler includes a light-weight swapping mechanism to allow for multiple threads to run on a core. The scheduler also handles the appropriate synchronization actions.

Memory Request Manager – Interface to the external architecture models. For the SynchroTrace Simulation Framework, the memory request manager packages the memory requests into requests for Ruby.

=Getting SynchroTrace:=

The SynchroTrace Simulation Framework is accessible through GitHub at: [https://github.com/VANDAL/SynchroTrace-gem5 git.io/synchrotrace]

Currently, there is only a repository for playing the synchronization-aware traces into the external cache and NoC models (Ruby and Garnet). We’ve included a few sample traces to test and explore this code-base. We are currently prepping the capture tool for release very soon.

The SynchroTrace publication can be found [[media:SynchroTrace.pdf‎|here]].

= Dependencies:=

The SynchroTrace Simulation Framework is integrated into Gem5′s cache and NoC simulators (Ruby and Garnet). Thus, SynchroTrace’s dependencies are based on Gem5′s dependencies. Please refer to http://www.gem5.org/Dependencies for more information.

SynchroTrace has been tested on Intel Xeon E5-based machines, running either RedHat Enterprise Linux 5, Centos 6, or Ubuntu 12.x operating systems. We have generated traces for PARSEC and Splash-2 benchmarks (up to 64 threads reliably) and ran them through our SynchroTrace Simulation Framework.

= Running the first time:=

Please follow the included Readme to compile SynchroTrace and run the sample traces for the first time.

= Also available at =
http://dpac.ece.drexel.edu/current-research-projects/synchrotrace/

File:ST Capture Replay.png

2019-08-12T16:29:42Z

Mdl45:

File:ST Capture Replay.pdf

2019-08-12T16:27:33Z

Mdl45:

Tutorials

2019-08-12T14:20:08Z

Mdl45: Add SynchroTrace tutorial links

== 2018 ==
=== IEEE International Green and Sustainable Computing Conference (IGSC) ===
'''October 22-24, Pittsburgh, Pennsylvania, USA'''

'''''Energy-Efficient and Secure Computing Systems ''''' (w/ Prof. Emre Salman, Stony Brook University)

== 2016 ==
=== IEEE International Symposium on Workload Characterization (IISWC) ===
'''September 25-27, Providence, Rhode Island, USA'''

[http://vlsi.ece.drexel.edu/index.php?title=Tutorials%3ASynchroTrace_Sigil_IISWC_2016 '''''Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation '''''] (w/ Prof. Mark Hempstead, Tufts University)

== 2015 ==
=== IEEE International Conference on Computer Design (ICCD) ===
'''October 18-21, New York City, New York, USA'''

[http://vlsi.ece.drexel.edu/index.php?title=Tutorials%3ASynchroTrace_Sigil_ICCD_2015 '''''Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation'''''] (w/ Prof. Mark Hempstead, Tufts University)

=== IEEE International Symposium on Workload Characterization (IISWC) ===
'''October 4-6, Atlanta, Georgia, USA'''

[http://vlsi.ece.drexel.edu/index.php?title=Tutorials%3ASynchroTrace_Sigil_IISWC_2015 '''''Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation'''''] (w/ Prof. Mark Hempstead, Tufts University)

=== IEEE International Symposium on Circuits and Systems (ISCAS) ===
'''May 24-27, Lisbon, Portugal'''

'''''Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances''''' (w/ Prof. Emre Salman, Stony Brook University)

== 2012 ==
=== ACM/IEEE International Conference on Computer-Aided Design (ICCAD) ===
'''November 5-8, San Jose, California, USA'''

'''''High Performance, Low Power Resonant Clocking''''' (w/ Prof. Matthew Guthaus, UCSC)

2018-03-11T17:53:26Z

Mdl45:

== GitHUB page ==
Drexel VANDAL GitHub: https://github.com/VANDAL

== SynchroTrace ==
[https://github.com/VANDAL/SynchroTrace-gem5 git.io/synchrotrace]

SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.).

For details and download information see: [[SynchroTrace]]

== Prism ==
[https://github.com/VANDAL/prism]

Prism is a super-cool™ framework for easily analyzing how an application runs.
If you want to easily look at memory operations, function traces, IOPs/FLOPs, et al, check out Prism.

We have used it internally for workload-guided EDA tool flows, on-chip routing, thread-mapping, and in the design of architectural simulators.

== SLECTS ==

Implementing a slew-driven clock tree synthesis methodology.

For details see: [[SLECTS]]

== Rotary Resonant Clock Synthesizer==

A rotary resonant clock synthesizer in Cadence.

For details see: [[RotaSyn]]

2018-01-19T20:28:04Z

Mdl45:

Main Page

2018-01-19T19:55:41Z

Mdl45:

__NOTOC__

[[File:VANDAL.png|super|200px]]

== Drexel VLSI and Architecture Laboratory ('''VANDAL''')==

Drexel VLSI and Architecture Laboratory consists of a research group of computer engineers, electrical engineers tackling multiple aspects of design, analysis, implementation of integrated circuits and chip architectures. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VLSI and Architecture group can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VLSI and Architecture group explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning, and Cryptocurrencies. Some of the most exciting projects currently ongoing involve:

#Charge Recovery Logic, which aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
#The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.
#The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
#With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).
#Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
#Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage.

[http://www.drexel.edu Drexel University]

[http://www.ece.drexel.edu Department of Electrical and Computer Engineering]

[http://maps.google.com/maps?f=q&source=s_q&hl=en&geocode=&q=3141+chestnut+Street+19104&sll=37.649034,-95.712891&sspn=37.558981,49.21875&ie=UTF8&ll=39.963241,-75.181932&spn=0.008948,0.012016&z=14&iwloc=A&amp 3141 Chestnut Street (map) ]

324 Bossone Research Center

Philadelphia, PA 19104



== [[People]] ==

=== Faculty ===

[[Baris Taskin| Baris Taskin (Biography, CV, Contact)]]

=== Ph.D. students ===

[[Leo Filippini]]

[[Ragh Kuttappa]]

[[Scott Lerner]]

[[Michael Lui]]

[[Vasil Pano]]

[[Karthik Sangaiah]]

=== Other researchers ===

See [[People]]

== [[Research]] ==

[[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]

[[Research#CMP-NoC Co-design|CMP-NoC Co-design]]

[[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]

[[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]

[[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]

[[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]

[[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]

== [[Publications]] ==

== [[Software]] ==

[https://github.com/VANDAL Github]

[[Software#SynchroTrace|SynchroTrace]]


== [[Seminars]] ==

== [[Tutorials]] ==

== [[Teaching]] ==

== [[News/Events]] ==

Main Page

2018-01-14T21:20:53Z

Mdl45:

__NOTOC__

[[File:VANDAL.png|super|200px]]

== Drexel VLSI and Architecture Laboratory ('''VANDAL''')==

[http://www.drexel.edu Drexel University]

[http://www.ece.drexel.edu Department of Electrical and Computer Engineering]

[http://maps.google.com/maps?f=q&source=s_q&hl=en&geocode=&q=3141+chestnut+Street+19104&sll=37.649034,-95.712891&sspn=37.558981,49.21875&ie=UTF8&ll=39.963241,-75.181932&spn=0.008948,0.012016&z=14&iwloc=A&amp 3141 Chestnut Street (map) ]

324 Bossone Research Center

Philadelphia, PA 19104



== [[People]] ==

=== Faculty ===

[[Baris Taskin| Baris Taskin (Biography, CV, Contact)]]

=== Ph.D. students ===

[[Leo Filippini]]

[[Ragh Kuttappa]]

[[Scott Lerner]]

[[Michael Lui]]

[[Vasil Pano]]

[[Karthik Sangaiah]]

=== Other researchers ===

See [[People]]

== [[Research]] ==

[[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]

[[Research#CMP-NoC Co-design|CMP-NoC Co-design]]

[[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]

[[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]

[[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]

[[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]

[[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]

== [[Publications]] ==

== [[Software]] ==

[https://github.com/VANDAL Github]

[[Software#SynchroTrace|SynchroTrace]]


== [[Seminars]] ==

== [[Tutorials]] ==

== [[Teaching]] ==

== [[News/Events]] ==

Main Page

2018-01-14T21:14:59Z

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[[File:VANDAL.png|super|200px]]

== Drexel VLSI and Architecture Laboratory ('''VANDAL''')==

[http://www.drexel.edu Drexel University]

[http://www.ece.drexel.edu Department of Electrical and Computer Engineering]

[http://maps.google.com/maps?f=q&source=s_q&hl=en&geocode=&q=3141+chestnut+Street+19104&sll=37.649034,-95.712891&sspn=37.558981,49.21875&ie=UTF8&ll=39.963241,-75.181932&spn=0.008948,0.012016&z=14&iwloc=A&amp 3141 Chestnut Street (map) ]

324 Bossone Research Center

Philadelphia, PA 19104



== [[People]] ==

=== Faculty ===

[[Baris Taskin| Baris Taskin (Biography, CV, Contact)]]

=== Ph.D. students ===

[[Leo Filippini]]

[[Ragh Kuttappa]]

[[Scott Lerner]]

[[Michael Lui]]

[[Vasil Pano]]

[[Karthik Sangaiah]]

=== Other researchers ===

See [[People]]

== [[Research]] ==

[[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]

[[Research#CMP-NoC Co-design|CMP-NoC Co-design]]

[[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]

[[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]

[[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]

[[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]

[[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]

== [[Publications]] ==

== [[Software]] ==

Drexel VANDAL GitHub: [https://github.com/VANDAL git.io/VANDAL]

[[Software#SynchroTrace|SynchroTrace]]


== [[Seminars]] ==

== [[Tutorials]] ==

== [[Teaching]] ==

== [[News/Events]] ==

Main Page

2018-01-14T21:14:07Z