VLSILab - User contributions [en]

File:Vasil Pano Resume.pdf

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2024-09-18T15:53:59Z

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Ragh: /* Journals */

== Conferences ==
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]
# Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
# Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020

* Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

File:Ragh kuttappa resume.pdf

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Ragh: Ragh uploaded a new version of File:Ragh kuttappa resume.pdf

Ragh Kuttappa

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Ragh: /* Journals */

[[File:Ragh.png|175px|thumb|right|Ragh Kuttappa]]

==Education==
'''Ph.D. in Electrical Engineering, ongoing''' <br>
:Drexel University, Philadelphia, PA, USA

'''M.S. in Electrical Engineering, 2015''' <br>
:San Francisco State University

'''Bachelor of Engineering, 2012''' <br>
:Visvesvaraya Technological University (VTU), Karnataka, India

==Research Interests==
* Resonant clocking technologies
* Adiabatic circuits
* Nanoscale circuits and systems
* Low-power design methodologies

'''Resonant clocking technologies ''' <br>
Resonant clocking is a low power clock generation and distribution solution for modern ICs. The main research focus is the design and implementation of rotary clocks that is interoperable within the traditional ASIC flow. Based on years of development and experience within Dr. Taskin's research group numerous products for rotary clocks are currently being developed to address future needs for energy efficient computing.

''1. RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer''

RotaSYN is a backend synthesis tool for rotary clocks. RotaSYN is demonstrated on publicly available designs and compared to traditionally clocked designs.
Check out our RotaSYN [https://ieeexplore.ieee.org/document/8653860 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:RotaSYN_Flow_ragh1.png|thumb|left|500px|RotaSYN Flow]] </li>

<li style="display: inline-block;"> [[File:aes_core.png|thumb|right|350px|AES core synthesized with RotaSYN]] </li>
</ul></div>

''2. Clock Synchronization for Multi-Die Systems''

Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. The underlying theme for the work is to synchronize chiplets that are in the “same clock domain”, regardless of homogeneous v.s. heterogeneous integration. Initial work and results of this work was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19]. An extension of the [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19] work with a complete methodology is published in [https://ieeexplore.ieee.org/document/9360308 TCAS-I].

<div><ul>
<li style="display: inline-block;"> [[File:Rotary_interposer_topology.png|thumb|left|245px|Active silicon interposer based synchronization topology for multi-die systems with resonant rotary clocks]] </li>
<li style="display: inline-block;"> [[File:MDS_flow.png|thumb|right|760px|Overall synchronization methodology for MDS]] </li>
<li style="display: inline-block;"> [[File:Rotary_interposer_die.png|thumb|right|360px|Multi-die system implemented with CORTEX M0 cores and resonant rotary clocks]] </li>
</ul></div>

''3. FOPAC: Flexible On-Chip Power and Clock''

In this work we propose a novel flexible on-chip power and clock (FOPAC) generation and distribution circuit to enable fast dynamic voltage and frequency scaling (DVFS). To fuse the power and clock design, the multiphase properties of resonant rotary clocks are utilized to design multiphase voltage regulators. We also propose a capacitance reuse technique with the fly cap of switched capacitor voltage regulators to modify the frequency of the global resonant rotary clock at runtime. Check out our FOPAC [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8815869&tag=1 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:Fopac.png|thumb|left|300px|FOPAC Architecture]] </li>

<li style="display: inline-block;"> [[File:fastdvfs.png|thumb|right|350px|Fast DVFS performance improvements and power savings]] </li>
</ul></div>

==Résumé==
[[media:Ragh_kuttappa_resume.pdf | Ragh Kuttappa (February 2021)]]

==Publications==

====Journals====
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636-1645, April 2021.
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Reliability Analysis of Spin Transfer Torque based Look up Tables under Process Variations and NBTI Aging", ''Elsevier Microelectronics Reliability Journal'', Vol. 62, pp. 156--166, July 2016.

====Conferences====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'' , February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019.
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019.
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019.
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019.
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.
# Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Comparative Analysis of Robustness of Spin Transfer Torque based Look Up Tables under Process Variations", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 606--609.

==Contact Information==
'''Address:''' <br>
3141 Chestnut Street <br>
Drexel University <br>
ECE Department <br>
Philadelphia, PA 19104 <br>

'''Office:''' Bossone 405 <br>
'''Email:''' fr67 [at the rate] drexel [period] edu <br>
'''Linkedin:''' [https://www.linkedin.com/in/ragh-kuttappa-06b4745b/ ragh/linkedin] <br>

Publications

2021-03-06T16:09:55Z

Ragh: /* Journals */

== Conferences ==
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636-1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]
# Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
# Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020

* Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Ragh Kuttappa

2021-02-23T15:47:06Z

Ragh: /* Research Interests */

[[File:Ragh.png|175px|thumb|right|Ragh Kuttappa]]

==Education==
'''Ph.D. in Electrical Engineering, ongoing''' <br>
:Drexel University, Philadelphia, PA, USA

'''M.S. in Electrical Engineering, 2015''' <br>
:San Francisco State University

'''Bachelor of Engineering, 2012''' <br>
:Visvesvaraya Technological University (VTU), Karnataka, India

==Research Interests==
* Resonant clocking technologies
* Adiabatic circuits
* Nanoscale circuits and systems
* Low-power design methodologies

'''Resonant clocking technologies ''' <br>
Resonant clocking is a low power clock generation and distribution solution for modern ICs. The main research focus is the design and implementation of rotary clocks that is interoperable within the traditional ASIC flow. Based on years of development and experience within Dr. Taskin's research group numerous products for rotary clocks are currently being developed to address future needs for energy efficient computing.

''1. RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer''

RotaSYN is a backend synthesis tool for rotary clocks. RotaSYN is demonstrated on publicly available designs and compared to traditionally clocked designs.
Check out our RotaSYN [https://ieeexplore.ieee.org/document/8653860 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:RotaSYN_Flow_ragh1.png|thumb|left|500px|RotaSYN Flow]] </li>

<li style="display: inline-block;"> [[File:aes_core.png|thumb|right|350px|AES core synthesized with RotaSYN]] </li>
</ul></div>

''2. Clock Synchronization for Multi-Die Systems''

Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. The underlying theme for the work is to synchronize chiplets that are in the “same clock domain”, regardless of homogeneous v.s. heterogeneous integration. Initial work and results of this work was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19]. An extension of the [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19] work with a complete methodology is published in [https://ieeexplore.ieee.org/document/9360308 TCAS-I].

<div><ul>
<li style="display: inline-block;"> [[File:Rotary_interposer_topology.png|thumb|left|245px|Active silicon interposer based synchronization topology for multi-die systems with resonant rotary clocks]] </li>
<li style="display: inline-block;"> [[File:MDS_flow.png|thumb|right|760px|Overall synchronization methodology for MDS]] </li>
<li style="display: inline-block;"> [[File:Rotary_interposer_die.png|thumb|right|360px|Multi-die system implemented with CORTEX M0 cores and resonant rotary clocks]] </li>
</ul></div>

''3. FOPAC: Flexible On-Chip Power and Clock''

In this work we propose a novel flexible on-chip power and clock (FOPAC) generation and distribution circuit to enable fast dynamic voltage and frequency scaling (DVFS). To fuse the power and clock design, the multiphase properties of resonant rotary clocks are utilized to design multiphase voltage regulators. We also propose a capacitance reuse technique with the fly cap of switched capacitor voltage regulators to modify the frequency of the global resonant rotary clock at runtime. Check out our FOPAC [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8815869&tag=1 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:Fopac.png|thumb|left|300px|FOPAC Architecture]] </li>

<li style="display: inline-block;"> [[File:fastdvfs.png|thumb|right|350px|Fast DVFS performance improvements and power savings]] </li>
</ul></div>

==Résumé==
[[media:Ragh_kuttappa_resume.pdf | Ragh Kuttappa (February 2021)]]

==Publications==

====Journals====
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021.
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Reliability Analysis of Spin Transfer Torque based Look up Tables under Process Variations and NBTI Aging", ''Elsevier Microelectronics Reliability Journal'', Vol. 62, pp. 156--166, July 2016.

====Conferences====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'' , February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019.
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019.
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019.
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019.
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.
# Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Comparative Analysis of Robustness of Spin Transfer Torque based Look Up Tables under Process Variations", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 606--609.

==Contact Information==
'''Address:''' <br>
3141 Chestnut Street <br>
Drexel University <br>
ECE Department <br>
Philadelphia, PA 19104 <br>

'''Office:''' Bossone 405 <br>
'''Email:''' fr67 [at the rate] drexel [period] edu <br>
'''Linkedin:''' [https://www.linkedin.com/in/ragh-kuttappa-06b4745b/ ragh/linkedin] <br>

Ragh Kuttappa

2021-02-23T15:46:08Z

Ragh: /* Research Interests */

[[File:Ragh.png|175px|thumb|right|Ragh Kuttappa]]

==Education==
'''Ph.D. in Electrical Engineering, ongoing''' <br>
:Drexel University, Philadelphia, PA, USA

'''M.S. in Electrical Engineering, 2015''' <br>
:San Francisco State University

'''Bachelor of Engineering, 2012''' <br>
:Visvesvaraya Technological University (VTU), Karnataka, India

==Research Interests==
* Resonant clocking technologies
* Adiabatic circuits
* Nanoscale circuits and systems
* Low-power design methodologies

'''Resonant clocking technologies ''' <br>
Resonant clocking is a low power clock generation and distribution solution for modern ICs. The main research focus is the design and implementation of rotary clocks that is interoperable within the traditional ASIC flow. Based on years of development and experience within Dr. Taskin's research group numerous products for rotary clocks are currently being developed to address future needs for energy efficient computing.

''1. RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer''

RotaSYN is a backend synthesis tool for rotary clocks. RotaSYN is demonstrated on publicly available designs and compared to traditionally clocked designs.
Check out our RotaSYN [https://ieeexplore.ieee.org/document/8653860 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:RotaSYN_Flow_ragh1.png|thumb|left|500px|RotaSYN Flow]] </li>

<li style="display: inline-block;"> [[File:aes_core.png|thumb|right|350px|AES core synthesized with RotaSYN]] </li>
</ul></div>

''2. Clock Synchronization for Multi-Die Systems''

Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. The underlying theme for the work in this project is to synchronize chiplets that are in the “same clock domain”, regardless of homogeneous v.s. heterogeneous integration. Initial work and results of this work was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19]. An extension of the [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19] work with a complete methodology is published in [https://ieeexplore.ieee.org/document/9360308 TCAS-I].

<div><ul>
<li style="display: inline-block;"> [[File:Rotary_interposer_topology.png|thumb|left|245px|Active silicon interposer based synchronization topology for multi-die systems with resonant rotary clocks]] </li>
<li style="display: inline-block;"> [[File:MDS_flow.png|thumb|right|760px|Overall synchronization methodology for MDS]] </li>
<li style="display: inline-block;"> [[File:Rotary_interposer_die.png|thumb|right|360px|Multi-die system implemented with CORTEX M0 cores and resonant rotary clocks]] </li>
</ul></div>

''3. FOPAC: Flexible On-Chip Power and Clock''

In this work we propose a novel flexible on-chip power and clock (FOPAC) generation and distribution circuit to enable fast dynamic voltage and frequency scaling (DVFS). To fuse the power and clock design, the multiphase properties of resonant rotary clocks are utilized to design multiphase voltage regulators. We also propose a capacitance reuse technique with the fly cap of switched capacitor voltage regulators to modify the frequency of the global resonant rotary clock at runtime. Check out our FOPAC [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8815869&tag=1 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:Fopac.png|thumb|left|300px|FOPAC Architecture]] </li>

<li style="display: inline-block;"> [[File:fastdvfs.png|thumb|right|350px|Fast DVFS performance improvements and power savings]] </li>
</ul></div>

==Résumé==
[[media:Ragh_kuttappa_resume.pdf | Ragh Kuttappa (February 2021)]]

==Publications==

====Journals====
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021.
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Reliability Analysis of Spin Transfer Torque based Look up Tables under Process Variations and NBTI Aging", ''Elsevier Microelectronics Reliability Journal'', Vol. 62, pp. 156--166, July 2016.

====Conferences====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'' , February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019.
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019.
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019.
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019.
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.
# Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Comparative Analysis of Robustness of Spin Transfer Torque based Look Up Tables under Process Variations", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 606--609.

==Contact Information==
'''Address:''' <br>
3141 Chestnut Street <br>
Drexel University <br>
ECE Department <br>
Philadelphia, PA 19104 <br>

'''Office:''' Bossone 405 <br>
'''Email:''' fr67 [at the rate] drexel [period] edu <br>
'''Linkedin:''' [https://www.linkedin.com/in/ragh-kuttappa-06b4745b/ ragh/linkedin] <br>

File:MDS flow.png

2021-02-23T15:42:32Z

Ragh:

Ragh Kuttappa

2021-02-23T15:41:04Z

Ragh: /* Research Interests */

[[File:Ragh.png|175px|thumb|right|Ragh Kuttappa]]

==Education==
'''Ph.D. in Electrical Engineering, ongoing''' <br>
:Drexel University, Philadelphia, PA, USA

'''M.S. in Electrical Engineering, 2015''' <br>
:San Francisco State University

'''Bachelor of Engineering, 2012''' <br>
:Visvesvaraya Technological University (VTU), Karnataka, India

==Research Interests==
* Resonant clocking technologies
* Adiabatic circuits
* Nanoscale circuits and systems
* Low-power design methodologies

'''Resonant clocking technologies ''' <br>
Resonant clocking is a low power clock generation and distribution solution for modern ICs. The main research focus is the design and implementation of rotary clocks that is interoperable within the traditional ASIC flow. Based on years of development and experience within Dr. Taskin's research group numerous products for rotary clocks are currently being developed to address future needs for energy efficient computing.

''1. RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer''

RotaSYN is a backend synthesis tool for rotary clocks. RotaSYN is demonstrated on publicly available designs and compared to traditionally clocked designs.
Check out our RotaSYN [https://ieeexplore.ieee.org/document/8653860 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:RotaSYN_Flow_ragh1.png|thumb|left|500px|RotaSYN Flow]] </li>

<li style="display: inline-block;"> [[File:aes_core.png|thumb|right|300px|AES core synthesized with RotaSYN]] </li>
</ul></div>

''2. Clock Synchronization for Multi-Die Systems''

Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. The underlying theme for the work in this project is to synchronize chiplets that are in the “same clock domain”, regardless of homogeneous v.s. heterogeneous integration. Initial work and results of this work was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19]. An extension of the [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19] work with a complete methodology is published in [https://ieeexplore.ieee.org/document/9360308 TCAS-I].

<div><ul>
<li style="display: inline-block;"> [[File:Rotary_interposer_topology.png|thumb|left|250px|Active silicon interposer based synchronization topology for multi-die systems with resonant rotary clocks]] </li>

<li style="display: inline-block;"> [[File:Rotary_interposer_die.png|thumb|right|300px|Multi-die system implemented with CORTEX M0 cores and resonant rotary clocks]] </li>
</ul></div>

''3. FOPAC: Flexible On-Chip Power and Clock''

In this work we propose a novel flexible on-chip power and clock (FOPAC) generation and distribution circuit to enable fast dynamic voltage and frequency scaling (DVFS). To fuse the power and clock design, the multiphase properties of resonant rotary clocks are utilized to design multiphase voltage regulators. We also propose a capacitance reuse technique with the fly cap of switched capacitor voltage regulators to modify the frequency of the global resonant rotary clock at runtime. Check out our FOPAC [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8815869&tag=1 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:Fopac.png|thumb|left|300px|FOPAC Architecture]] </li>

<li style="display: inline-block;"> [[File:fastdvfs.png|thumb|right|300px|Fast DVFS performance improvements and power savings]] </li>
</ul></div>

==Résumé==
[[media:Ragh_kuttappa_resume.pdf | Ragh Kuttappa (February 2021)]]

==Publications==

====Journals====
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021.
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Reliability Analysis of Spin Transfer Torque based Look up Tables under Process Variations and NBTI Aging", ''Elsevier Microelectronics Reliability Journal'', Vol. 62, pp. 156--166, July 2016.

====Conferences====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'' , February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019.
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019.
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019.
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019.
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.
# Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Comparative Analysis of Robustness of Spin Transfer Torque based Look Up Tables under Process Variations", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 606--609.

==Contact Information==
'''Address:''' <br>
3141 Chestnut Street <br>
Drexel University <br>
ECE Department <br>
Philadelphia, PA 19104 <br>

'''Office:''' Bossone 405 <br>
'''Email:''' fr67 [at the rate] drexel [period] edu <br>
'''Linkedin:''' [https://www.linkedin.com/in/ragh-kuttappa-06b4745b/ ragh/linkedin] <br>

Publications

2021-02-23T14:18:41Z

Ragh: /* Conferences */

== Conferences ==
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]
# Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
# Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020

* Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Publications

2021-02-23T14:17:35Z

Ragh: /* Journals */

== Conferences ==
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]
# Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
# Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020

* Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Ragh Kuttappa

2021-02-02T14:27:41Z

Ragh: /* Résumé */

[[File:Ragh.png|175px|thumb|right|Ragh Kuttappa]]

==Education==
'''Ph.D. in Electrical Engineering, ongoing''' <br>
:Drexel University, Philadelphia, PA, USA

'''M.S. in Electrical Engineering, 2015''' <br>
:San Francisco State University

'''Bachelor of Engineering, 2012''' <br>
:Visvesvaraya Technological University (VTU), Karnataka, India

==Research Interests==
* Resonant clocking technologies
* Adiabatic circuits
* Nanoscale circuits and systems
* Low-power design methodologies

'''Resonant clocking technologies ''' <br>
Resonant clocking is a low power clock generation and distribution solution for modern ICs. The main research focus is the design and implementation of rotary clocks that is interoperable within the traditional ASIC flow. Based on years of development and experience within Dr. Taskin's research group numerous products for rotary clocks are currently being developed to address future needs for energy efficient computing.

''1. RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer''

RotaSYN is a backend synthesis tool for rotary clocks. RotaSYN is demonstrated on publicly available designs and compared to traditionally clocked designs.
Check out our RotaSYN [https://ieeexplore.ieee.org/document/8653860 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:RotaSYN_Flow_ragh1.png|thumb|left|500px|RotaSYN Flow]] </li>

<li style="display: inline-block;"> [[File:aes_core.png|thumb|right|300px|AES core synthesized with RotaSYN]] </li>
</ul></div>

''2. Robust Low Power Clock Synchronization for Multi-Die Systems''

Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. This paper was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19].

<div><ul>
<li style="display: inline-block;"> [[File:Rotary_interposer_topology.png|thumb|left|250px|Active silicon interposer based synchronization topology for multi-die systems with resonant rotary clocks]] </li>

<li style="display: inline-block;"> [[File:Rotary_interposer_die.png|thumb|right|300px|Multi-die system implemented with CORTEX M0 cores and resonant rotary clocks]] </li>
</ul></div>

''3. FOPAC: Flexible On-Chip Power and Clock''

In this work we propose a novel flexible on-chip power and clock (FOPAC) generation and distribution circuit to enable fast dynamic voltage and frequency scaling (DVFS). To fuse the power and clock design, the multiphase properties of resonant rotary clocks are utilized to design multiphase voltage regulators. We also propose a capacitance reuse technique with the fly cap of switched capacitor voltage regulators to modify the frequency of the global resonant rotary clock at runtime. Check out our FOPAC [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8815869&tag=1 PAPER] published in TCAS-I.

<div><ul>
<li style="display: inline-block;"> [[File:Fopac.png|thumb|left|300px|FOPAC Architecture]] </li>

<li style="display: inline-block;"> [[File:fastdvfs.png|thumb|right|300px|Fast DVFS performance improvements and power savings]] </li>
</ul></div>

==Résumé==
[[media:Ragh_kuttappa_resume.pdf | Ragh Kuttappa (February 2021)]]

==Publications==

====Journals====
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021.
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Reliability Analysis of Spin Transfer Torque based Look up Tables under Process Variations and NBTI Aging", ''Elsevier Microelectronics Reliability Journal'', Vol. 62, pp. 156--166, July 2016.

====Conferences====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'' , February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019.
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019.
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019.
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019.
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018.
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.
# Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.
# Ragh Kuttappa, Houman Homayoun, Hassan Salmani and Hamid Mahmoodi, "Comparative Analysis of Robustness of Spin Transfer Torque based Look Up Tables under Process Variations", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 606--609.

==Contact Information==
'''Address:''' <br>
3141 Chestnut Street <br>
Drexel University <br>
ECE Department <br>
Philadelphia, PA 19104 <br>

'''Office:''' Bossone 405 <br>
'''Email:''' fr67 [at the rate] drexel [period] edu <br>
'''Linkedin:''' [https://www.linkedin.com/in/ragh-kuttappa-06b4745b/ ragh/linkedin] <br>

2020-01-07T13:13:58Z

Ragh: /* Conferences */

== Conferences ==
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Vasil Pano, Ph.D. Dissertation: Wireless Network on Chip for Multi-Die Systems, 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007