VLSILab - User contributions [en]

Scott Lerner

2018-12-03T16:36:32Z

Scott: /* Journals */

[[File:scott_pic.jpg|right|border|frame|[[Scott Lerner]]|25px]]

== Education ==
'''PhD in Electrical Engineering expected graduation mid-2019''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Electrical Engineering, 2014''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Computer Engineering, 2014''' 
:Drexel University, Philadelphia, PA.

== Research Interests ==
My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging
computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and
internet-of-things.

== Curriculum Vitae ==
[[media:Scott_cv.pdf | Scott Lerner CV (Dec 2018)]]

== Journals ==
# S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572
# S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664
# S. Lerner, and B.Taskin, “Workload-Aware ASIC Design Considering Lithography Information”, in preparation for submission, 2019.

== Papers ==
# S. Lerner and B.Taskin, “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, Proceedings of the IEEE International Green and Sustainable Computing (IGSC) Conference, Oct. 2018.
# S. Lerner, V. Pano, and B.Taskin, “NoC Router Lifetime Improvement using Per-Port Router Utilization”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
# V. Pano, S. Lerner, and B.Taskin, “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, “Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2017.
# S. Lerner and B.Taskin, “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, Proceedings of the International Symposium on VLSI (ISVLSI), Jul. 2017.
# S. Lerner, E. Leggett, and B.Taskin, “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, Proceedings of the System Level Interconnect Prediction (SLIP), Jun. 2017.
# S. Lerner and B.Taskin, “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, Proceedings of the International Symposium on Quality Electronic Design (ISQED), Mar. 2017.
# S. Nilakantan, S. Lerner, M. Hempstead, and B. Taskin, “Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation”, '''Nominated for best paper''' at the IEEE International Conference on VLSI Design (VLSID), Jan. 2015.
# C. Sitik, S. Lerner, and B. Taskin, “Timing Characterization of Clock Buffers for Clock Tree Synthesis”, Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2014.

== Presentations ==
# “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, International Green and Sustainable Computing Conference, Pittsburgh, PA, October 2018.
# “NoC Router Lifetime Improvement using Per-Port Router Utilization”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
# “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
# “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, International Symposium on VLSI, Bochum, Germany, July 2017.5. “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, System Level Interconnect Prediction, Austin, Texas, June 2017.
# “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, International Symposium on Quality Electronic Design, Santa Clara, California, March 2017.

# Enhancements in Low Voltage and High Performance Clock Distribution Networks, SRC Innovation and Intelligent Internet of Things, November 2016.
# High-Frequency Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
# Internal Node Relaxation for Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
# Workload-Aware EDA, IEEE CE Graduate Symposium, February 2016.
# Wireless Network-on-Chip, Mid-Atlantic ASEE, November 2014
# Arduino Robotics in the Classroom, Mid-Atlantic ASEE, November 2014
# Low-Power Clock Network Designs, IEEE Design Automation Conference, June 2014
# Low Swing Clocking Algorithm for 20nm FinFET Technology, Upsilon Pi Epsilon Research Reception, February 2014.
# Sub-45nm Interconnect Modeling, Drexel IEEE Graduate Forum, February 2014.
# MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014.
# Low-Power/High-Performance Clock Network Design for Microprocessors, Upsilon Pi Epsilon Research Reception, February 2013.

== Awards ==
# IGSC Best Presentation Nominee, 2018
# IGSC Travel Award, 2018
# Weggel Family Fellowship, 2018
# Frank and Agnes Seaman Endowed Fellowship, 2016
# NSF Graduate Research Fellowship Program (GRFP), 2015-2018
# National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
# Nihat Bilgutay Award, 2015
# TCVLSI Travel Award, 2015
# NSF Research Experience for Undergraduate (REU) recipient 2014
# A. Richard Newton Young Fellow Award 2014, 2015, 2016, 2017, 2018
# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# Doctor Thomas Moore Endowed Grant 2014
# Dean's List, 2009-2014

== Selected Projects ==
# Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014 '''Dean's Choice Award'''

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 324 
Philadelphia 
Pennsylvania 19104 

'''Phone:''' (863) 307-6194 
'''Fax:''' (215) 895-1695 
'''Email: '''spl29@drexel.edu

Scott Lerner

2018-12-03T16:35:52Z

Scott:

[[File:scott_pic.jpg|right|border|frame|[[Scott Lerner]]|25px]]

== Education ==
'''PhD in Electrical Engineering expected graduation mid-2019''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Electrical Engineering, 2014''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Computer Engineering, 2014''' 
:Drexel University, Philadelphia, PA.

== Research Interests ==
My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging
computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and
internet-of-things.

== Curriculum Vitae ==
[[media:Scott_cv.pdf | Scott Lerner CV (Dec 2018)]]

== Journals ==
# S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in
IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572
# S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”,
in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664
# S. Lerner, and B.Taskin, “Workload-Aware ASIC Design Considering Lithography Information”, in preparation for
submission, 2019.

== Papers ==
# S. Lerner and B.Taskin, “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, Proceedings of the IEEE International Green and Sustainable Computing (IGSC) Conference, Oct. 2018.
# S. Lerner, V. Pano, and B.Taskin, “NoC Router Lifetime Improvement using Per-Port Router Utilization”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
# V. Pano, S. Lerner, and B.Taskin, “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, “Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2017.
# S. Lerner and B.Taskin, “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, Proceedings of the International Symposium on VLSI (ISVLSI), Jul. 2017.
# S. Lerner, E. Leggett, and B.Taskin, “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, Proceedings of the System Level Interconnect Prediction (SLIP), Jun. 2017.
# S. Lerner and B.Taskin, “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, Proceedings of the International Symposium on Quality Electronic Design (ISQED), Mar. 2017.
# S. Nilakantan, S. Lerner, M. Hempstead, and B. Taskin, “Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation”, '''Nominated for best paper''' at the IEEE International Conference on VLSI Design (VLSID), Jan. 2015.
# C. Sitik, S. Lerner, and B. Taskin, “Timing Characterization of Clock Buffers for Clock Tree Synthesis”, Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2014.

== Presentations ==
# “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, International Green and Sustainable Computing Conference, Pittsburgh, PA, October 2018.
# “NoC Router Lifetime Improvement using Per-Port Router Utilization”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
# “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
# “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, International Symposium on VLSI, Bochum, Germany, July 2017.5. “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, System Level Interconnect Prediction, Austin, Texas, June 2017.
# “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, International Symposium on Quality Electronic Design, Santa Clara, California, March 2017.

# Enhancements in Low Voltage and High Performance Clock Distribution Networks, SRC Innovation and Intelligent Internet of Things, November 2016.
# High-Frequency Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
# Internal Node Relaxation for Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
# Workload-Aware EDA, IEEE CE Graduate Symposium, February 2016.
# Wireless Network-on-Chip, Mid-Atlantic ASEE, November 2014
# Arduino Robotics in the Classroom, Mid-Atlantic ASEE, November 2014
# Low-Power Clock Network Designs, IEEE Design Automation Conference, June 2014
# Low Swing Clocking Algorithm for 20nm FinFET Technology, Upsilon Pi Epsilon Research Reception, February 2014.
# Sub-45nm Interconnect Modeling, Drexel IEEE Graduate Forum, February 2014.
# MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014.
# Low-Power/High-Performance Clock Network Design for Microprocessors, Upsilon Pi Epsilon Research Reception, February 2013.

== Awards ==
# IGSC Best Presentation Nominee, 2018
# IGSC Travel Award, 2018
# Weggel Family Fellowship, 2018
# Frank and Agnes Seaman Endowed Fellowship, 2016
# NSF Graduate Research Fellowship Program (GRFP), 2015-2018
# National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
# Nihat Bilgutay Award, 2015
# TCVLSI Travel Award, 2015
# NSF Research Experience for Undergraduate (REU) recipient 2014
# A. Richard Newton Young Fellow Award 2014, 2015, 2016, 2017, 2018
# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# Doctor Thomas Moore Endowed Grant 2014
# Dean's List, 2009-2014

== Selected Projects ==
# Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014 '''Dean's Choice Award'''

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 324 
Philadelphia 
Pennsylvania 19104 

'''Phone:''' (863) 307-6194 
'''Fax:''' (215) 895-1695 
'''Email: '''spl29@drexel.edu

Scott Lerner

2018-12-03T16:04:58Z

Scott: /* Curriculum Vitae */

[[File:scott_pic.jpg|right|border|frame|[[Scott Lerner]]|25px]]

== Education ==
'''PhD in Electrical Engineering expected graduation mid-2019''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Electrical Engineering, 2014''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Computer Engineering, 2014''' 
:Drexel University, Philadelphia, PA.

== Research Interests ==
My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging
computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and
internet-of-things.

== Curriculum Vitae ==
[[media:Scott_cv.pdf | Scott Lerner CV (Dec 2018)]]

== Selected Publications ==
# S. Lerner, V. Pano, B.Taskin, NoC Router Lifetime Improvement using Per-Port Router Utilization, Proceedings of the International Symposium on Circuit and Systems (ISCAS) 2018.
# V. Pano, S. Lerner, B.Taskin, Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement, Proceedings of the International Symposium on Circuit and Systems (ISCAS) 2018.
# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI, presented at International Symposium on Circuits and Systems (ISCAS), May 2017.
# S. Lerner, B.Taskin, WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS, presented at International Symposium on VLSI (ISVLSI), July 2017.
# S. Lerner, E. Leggett, and B.Taskin, Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers, presented at System Level Interconnect Prediction (SLIP) 2017.
# S. Lerner, B.Taskin, BSST-DME: Slew Merging Region Propagation for Bounded CTS, submitted to International Conference on Computer Aided Design (ICCAD) 2017.
# S. Lerner, B.Taskin, Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors, Proceedings of the International Symposium on Quality Electronic Design, March 2017.
# C. Sitik, W. Liu, S. Lerner, E. Salman, and B. Taskin, An Improved Methodology for Low Voltage Gated Clock Tree Synthesis, submitted to International Symposium on Physical Design (ISPD) 2017.
# S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015. '''Best Paper Nominee'''
# C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014.

== Poster Presentations ==
# S. Lerner, B. Taskin Enhancements in Low Voltage and High Performance Clock Distribution Networks, Poster presented at SRC Innovation and Intelligent Internet of Things, Nov. 2016.
# A. Milani, S. Lerner, B. Taskin High-Frequency Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
# R. Farnesi, S. Lerner, B. Taskin Internal Node Relaxation for Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
# S. Lerner, B. Taskin Workload-Aware EDA, Presentation given at IEEE CE Graduate Symposium, Feb. 2016.
# S. Lerner, V. Pano, and B. Taskin, Wireless Network-on-Chip, Poster to be presented at Mid-Atlantic ASEE, November 2014
# S. Lerner, Arduino Robotics in the Classroom, Poster to be presented at Mid-Atlantic ASEE, November 2014
# Scott Lerner, and Baris Taskin, Low-Power Clock Network Designs, Poster presented at IEEE Design Automation Conference, June 2014
# S. Lerner, C. Sitik, and B. Taskin, Low Swing Clocking Algorithm for 20nm FinFET Technology, Poster presented at Upsilon Pi Epsilon Research Reception, February 2014.
# S. Lerner, C. Sitik, and B. Taskin, Sub-45nm Interconnect Modeling, Poster presented at Drexel IEEE Graduate Forum, February 2014.
# S. Lerner, R. Welliver, B. Derveni, C. Schoenfield, I. Yilmaz, MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, presented at Philly Codefest, February 2014.
# C. Sitik, S. Lerner, and B. Taskin, Low-Power/High-Performance Clock Network Design for Microprocessors, Poster presented at Upsilon Pi Epsilon Research Reception, February 2013.

== Awards ==
# Frank and Agnes Seaman Endowed Fellowship, 2016
# NSF Graduate Research Fellowship Program (GRFP), 2015
# National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
# Nihat Bilgutay Award, 2015
# TCVLSI Travel Award, 2015
# NSF Research Experience for Undergraduate (REU) recipient 2014
# A. Richard Newton Young Fellow Award to attend to IEEE/ACM DAC 2014, 2015, 2016, 2017
# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# Doctor Thomas Moore Endowed Grant 2014
# Dean's List, 2009, 2010, 2011, 2012, 2013, 2014

== Selected Projects ==
# Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014 '''Dean's Choice Award'''

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 324 
Philadelphia 
Pennsylvania 19104 

'''Phone:''' (863) 307-6194 
'''Fax:''' (215) 895-1695 
'''Email: '''spl29@drexel.edu

2018-06-06T14:07:57Z

Scott:

Publications

2018-01-24T16:11:10Z

Scott:

== Conferences ==
#Scott Lerner, Vasil Pano, and Baris Taskin, “NoC Router Lifetime Improvement using Per-Port Router Utilization,” (to appear) in "Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)", May 2018.
#Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” (to appear) in "Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)", May 2018.
#Leo Filippini, Lunal Khuon, and Baris Taskin, “Charge Recovery Implementation of an Analog Comparator: Initial Results,” in Proc. IEEE 60th Int. Midwest Symp. Circuits and Systems (MWSCAS), pp. 1505–1508, Aug. 2017.
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193.
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470.
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017.
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4.
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617.
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384.
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345.
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9.
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.
# Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|"Multi-Corner Multi-Voltage Domain Clock Mesh Design"]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.
# Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|"Skew-Bounded Low Swing Clock Tree Optimization"]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.
# Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|"Multi-Voltage Domain Clock Mesh Design"]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.
# Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|"Wireless Interconnects for Inter-tier Communication on 3-D ICs"]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.
# Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|"Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC"]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.
# Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|"Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits"]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.
# Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|"Electromagnetic Compatibility of CMOS On-chip Antennas"]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.
# Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|"Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs"]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.
# Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|"Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation"]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.
# Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|"Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects"]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.
# Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|"Leakage Current Analysis for Intra-Chip Wireless Interconnects"]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.

== Journals ==

# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks," ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011.
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011.
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009.
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>

== Tutorials ==

* [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).

* [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).

* [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).

* Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).

* High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).

== Thesis and Dissertations ==

* A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Main Page

2018-01-24T16:09:10Z

Scott:

__NOTOC__

[[File:VANDAL.png|right|super|200px]]

== Drexel VLSI and Architecture Laboratory ('''VANDAL''')==

Drexel VLSI and Architecture Laboratory consists of a research group of computer engineers, electrical engineers tackling multiple aspects of design, analysis, implementation of integrated circuits and chip architectures. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VLSI and Architecture group can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VLSI and Architecture group explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning, and Cryptocurrencies. Some of the most exciting projects currently ongoing involve:

#Charge Recovery Logic, which aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
#The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.
#The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
#With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).
#Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
#Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage.

[http://www.drexel.edu Drexel University]

[http://www.ece.drexel.edu Department of Electrical and Computer Engineering]

[http://maps.google.com/maps?f=q&source=s_q&hl=en&geocode=&q=3141+chestnut+Street+19104&sll=37.649034,-95.712891&sspn=37.558981,49.21875&ie=UTF8&ll=39.963241,-75.181932&spn=0.008948,0.012016&z=14&iwloc=A&amp 3141 Chestnut Street (map) ]

324 Bossone Research Center

Philadelphia, PA 19104



== [[People]] ==

=== Faculty ===

[[Baris Taskin| Baris Taskin (Biography, CV, Contact)]]

=== Ph.D. students ===

[[Leo Filippini]]

[[Ragh Kuttappa]]

[[Scott Lerner]]

[[Michael Lui]]

[[Vasil Pano]]

[[Karthik Sangaiah]]

=== Other researchers ===

See [[People]]

== [[Research]] ==

[[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]

[[Research#CMP-NoC Co-design|CMP-NoC Co-design]]

[[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]

[[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]

[[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]

[[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]

[[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]

== [[Publications]] ==

== [[Software]] ==

[https://github.com/VANDAL Github]

[[Software#SynchroTrace|SynchroTrace]]


== [[Seminars]] ==

== [[Tutorials]] ==

== [[Teaching]] ==

== [[News/Events]] ==

Scott Lerner

2017-06-14T12:57:43Z

Scott: /* Curriculum Vitae */

[[File:scott_pic.jpg|right|border|frame|[[Scott Lerner]]|25px]]

== Education ==
'''PhD in Electrical Engineering expected graduation 2018''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Electrical Engineering, 2014''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Computer Engineering, 2014''' 
:Drexel University, Philadelphia, PA.

== Research Interests ==
* Physical Design including Floorplanning, Placement and Routing
* Interconnect Modeling
* Parametric on-chip Variation
* Low-power Clock Tree Topologies
* Low-power Clock Gating
* Software Analysis for Hardware Reliability

== Curriculum Vitae ==
[[media:Scott_CV_v8.pdf | Scott Lerner CV (Jun 2017)]]

== Selected Publications ==
# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI, to be presented at International Symposium on Circuits and Systems (ISCAS), May 2017.
# S. Lerner, B.Taskin, WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS, to be presented at International Symposium on VLSI (ISVLSI), July 2017.
# S. Lerner, E. Leggett, and B.Taskin, Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers, to be presented at System Level Interconnect Prediction (SLIP) 2017.
# S. Lerner, B.Taskin, BSST-DME: Slew Merging Region Propagation for Bounded CTS, submitted to International Conference on Computer Aided Design (ICCAD) 2017.
# S. Lerner, B.Taskin, Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors, Proceedings of the International Symposium on Quality Electronic Design, March 2017.
# C. Sitik, W. Liu, S. Lerner, E. Salman, and B. Taskin, An Improved Methodology for Low Voltage Gated Clock Tree Synthesis, submitted to International Symposium on Physical Design (ISPD) 2017.
# S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015. '''Best Paper Nominee'''
# C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014.

== Poster Presentations ==
# S. Lerner, B. Taskin Enhancements in Low Voltage and High Performance Clock Distribution Networks, Poster presented at SRC Innovation and Intelligent Internet of Things, Nov. 2016.
# A. Milani, S. Lerner, B. Taskin High-Frequency Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
# R. Farnesi, S. Lerner, B. Taskin Internal Node Relaxation for Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
# S. Lerner, B. Taskin Workload-Aware EDA, Presentation given at IEEE CE Graduate Symposium, Feb. 2016.
# S. Lerner, V. Pano, and B. Taskin, Wireless Network-on-Chip, Poster to be presented at Mid-Atlantic ASEE, November 2014
# S. Lerner, Arduino Robotics in the Classroom, Poster to be presented at Mid-Atlantic ASEE, November 2014
# Scott Lerner, and Baris Taskin, Low-Power Clock Network Designs, Poster presented at IEEE Design Automation Conference, June 2014
# S. Lerner, C. Sitik, and B. Taskin, Low Swing Clocking Algorithm for 20nm FinFET Technology, Poster presented at Upsilon Pi Epsilon Research Reception, February 2014.
# S. Lerner, C. Sitik, and B. Taskin, Sub-45nm Interconnect Modeling, Poster presented at Drexel IEEE Graduate Forum, February 2014.
# S. Lerner, R. Welliver, B. Derveni, C. Schoenfield, I. Yilmaz, MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, presented at Philly Codefest, February 2014.
# C. Sitik, S. Lerner, and B. Taskin, Low-Power/High-Performance Clock Network Design for Microprocessors, Poster presented at Upsilon Pi Epsilon Research Reception, February 2013.

== Awards ==
# Frank and Agnes Seaman Endowed Fellowship, 2016
# NSF Graduate Research Fellowship Program (GRFP), 2015
# National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
# Nihat Bilgutay Award, 2015
# TCVLSI Travel Award, 2015
# NSF Research Experience for Undergraduate (REU) recipient 2014
# A. Richard Newton Young Fellow Award to attend to IEEE/ACM DAC 2014, 2015, 2016, 2017
# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# Doctor Thomas Moore Endowed Grant 2014
# Dean's List, 2009, 2010, 2011, 2012, 2013, 2014

== Selected Projects ==
# Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014 '''Dean's Choice Award'''

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 324 
Philadelphia 
Pennsylvania 19104 

'''Phone:''' (863) 307-6194 
'''Fax:''' (215) 895-1695 
'''Email: '''spl29@drexel.edu

File:Scott CV v8.pdf

2017-06-14T12:57:12Z

Scott:

Scott Lerner

2017-06-14T12:55:40Z

Scott:

[[File:scott_pic.jpg|right|border|frame|[[Scott Lerner]]|25px]]

== Education ==
'''PhD in Electrical Engineering expected graduation 2018''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Electrical Engineering, 2014''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Computer Engineering, 2014''' 
:Drexel University, Philadelphia, PA.

== Research Interests ==
* Physical Design including Floorplanning, Placement and Routing
* Interconnect Modeling
* Parametric on-chip Variation
* Low-power Clock Tree Topologies
* Low-power Clock Gating
* Software Analysis for Hardware Reliability

== Curriculum Vitae ==
[[media:Scott_CV_v1.pdf | Scott Lerner CV (Feb 2014)]]

== Selected Publications ==
# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI, to be presented at International Symposium on Circuits and Systems (ISCAS), May 2017.
# S. Lerner, B.Taskin, WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS, to be presented at International Symposium on VLSI (ISVLSI), July 2017.
# S. Lerner, E. Leggett, and B.Taskin, Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers, to be presented at System Level Interconnect Prediction (SLIP) 2017.
# S. Lerner, B.Taskin, BSST-DME: Slew Merging Region Propagation for Bounded CTS, submitted to International Conference on Computer Aided Design (ICCAD) 2017.
# S. Lerner, B.Taskin, Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors, Proceedings of the International Symposium on Quality Electronic Design, March 2017.
# C. Sitik, W. Liu, S. Lerner, E. Salman, and B. Taskin, An Improved Methodology for Low Voltage Gated Clock Tree Synthesis, submitted to International Symposium on Physical Design (ISPD) 2017.
# S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015. '''Best Paper Nominee'''
# C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014.

== Poster Presentations ==
# S. Lerner, B. Taskin Enhancements in Low Voltage and High Performance Clock Distribution Networks, Poster presented at SRC Innovation and Intelligent Internet of Things, Nov. 2016.
# A. Milani, S. Lerner, B. Taskin High-Frequency Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
# R. Farnesi, S. Lerner, B. Taskin Internal Node Relaxation for Clock Tree Synthesis, Poster presented at Drexel STAR Symposium, Aug. 2016.
# S. Lerner, B. Taskin Workload-Aware EDA, Presentation given at IEEE CE Graduate Symposium, Feb. 2016.
# S. Lerner, V. Pano, and B. Taskin, Wireless Network-on-Chip, Poster to be presented at Mid-Atlantic ASEE, November 2014
# S. Lerner, Arduino Robotics in the Classroom, Poster to be presented at Mid-Atlantic ASEE, November 2014
# Scott Lerner, and Baris Taskin, Low-Power Clock Network Designs, Poster presented at IEEE Design Automation Conference, June 2014
# S. Lerner, C. Sitik, and B. Taskin, Low Swing Clocking Algorithm for 20nm FinFET Technology, Poster presented at Upsilon Pi Epsilon Research Reception, February 2014.
# S. Lerner, C. Sitik, and B. Taskin, Sub-45nm Interconnect Modeling, Poster presented at Drexel IEEE Graduate Forum, February 2014.
# S. Lerner, R. Welliver, B. Derveni, C. Schoenfield, I. Yilmaz, MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, presented at Philly Codefest, February 2014.
# C. Sitik, S. Lerner, and B. Taskin, Low-Power/High-Performance Clock Network Design for Microprocessors, Poster presented at Upsilon Pi Epsilon Research Reception, February 2013.

== Awards ==
# Frank and Agnes Seaman Endowed Fellowship, 2016
# NSF Graduate Research Fellowship Program (GRFP), 2015
# National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
# Nihat Bilgutay Award, 2015
# TCVLSI Travel Award, 2015
# NSF Research Experience for Undergraduate (REU) recipient 2014
# A. Richard Newton Young Fellow Award to attend to IEEE/ACM DAC 2014, 2015, 2016, 2017
# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# Doctor Thomas Moore Endowed Grant 2014
# Dean's List, 2009, 2010, 2011, 2012, 2013, 2014

== Selected Projects ==
# Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014 '''Dean's Choice Award'''

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 324 
Philadelphia 
Pennsylvania 19104 

'''Phone:''' (863) 307-6194 
'''Fax:''' (215) 895-1695 
'''Email: '''spl29@drexel.edu

Publications

2017-04-25T16:33:26Z

Scott: /* Conferences */

== Conferences ==
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", (to appear) ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2017.
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", (to appear) ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017.
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", (to appear) ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017.
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", (to appear) ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017.
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486.
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403.
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9.
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.
# Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|"Multi-Corner Multi-Voltage Domain Clock Mesh Design"]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.
# Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|"Skew-Bounded Low Swing Clock Tree Optimization"]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.
# Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|"Multi-Voltage Domain Clock Mesh Design"]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.
# Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|"Wireless Interconnects for Inter-tier Communication on 3-D ICs"]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.
# Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|"Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC"]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.
# Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|"Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits"]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.
# Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|"Electromagnetic Compatibility of CMOS On-chip Antennas"]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.
# Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|"Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs"]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.
# Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|"Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation"]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.
# Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|"Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects"]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.
# Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|"Leakage Current Analysis for Intra-Chip Wireless Interconnects"]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.

== Journals ==

# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks," ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011.
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011.
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009.
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>

== Tutorials ==

* [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).

* [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).

* [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).

* Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).

* High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).

== Thesis and Dissertations ==

* A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Publications

2017-01-19T15:59:14Z

Scott: /* Conferences */

== Conferences ==
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors". (to appear) ''International Symposium on Quality Electronic Design (ISQED)'', March 2017
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice". (to appear) ''International Symposium on Quality Electronic Design (ISQED)'', March 2017
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545.
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598.
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372.
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510.
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445.
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6.
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” [[media:SynchroTrace.pdf‎|SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation]]”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287.
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134.
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140.
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749.
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520.
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9.
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482.
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.
# Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13_2.pdf‎|"Multi-Corner Multi-Voltage Domain Clock Mesh Design"]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.
# Can Sitik and Baris Taskin, [[media:Can_GLSVLSI13.pdf‎|"Skew-Bounded Low Swing Clock Tree Optimization"]], ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''.
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350.
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697.
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745.
# Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|"Multi-Voltage Domain Clock Mesh Design"]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126.
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122.
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643.
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142.
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24.
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278.
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011.
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75.
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222.
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943.

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138.
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460.

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214.
# Ankit More and Baris Taskin, [[media:EuMIC_2010_Ankit.pdf|"Wireless Interconnects for Inter-tier Communication on 3-D ICs"]], ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108.
# Ankit More and Baris Taskin, [[media:SoCC_2010_Ankit.pdf|"Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC"]], ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452.
# Ankit More and Baris Taskin, [[media:MMS_2010_Ankit.pdf|"Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits"]], ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010.
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116.
# Ankit More and Baris Taskin, [[media:APS_2010_Ankit.pdf|"Electromagnetic Compatibility of CMOS On-chip Antennas"]], ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4.
# Ankit More and Baris Taskin, [[media:ISVLSI_2010_Ankit.pdf|"Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs"]], ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231.
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22.
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472.
# Ankit More and Baris Taskin, [[media:Slip_2010_Ankit.pdf|"Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation"]], ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41.
# Ankit More and Baris Taskin, [[media:Gls_2010_Ankit.pdf|"Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects"]], ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416.
# Ankit More and Baris Taskin, [[media:ISQED_2010_Ankit.pdf|"Leakage Current Analysis for Intra-Chip Wireless Interconnects"]], ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417.
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223.
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236.
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168.
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150.
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235.
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593.
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119.
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''.
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445.
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61.
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66.
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490.
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265.
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305.
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54.
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610.
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606.
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620.
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117.
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362.

== Journals ==

# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks," ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016.
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015.
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015.
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012.
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012.
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011.
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011.
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011.
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676.
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''.
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809.
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009.
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009.
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009.
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008.
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006.
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004.

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>

== Tutorials ==

* [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).

* [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).

* [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).

* Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).

* High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).

== Thesis and Dissertations ==

* A. Can Sitik, Ph.D. Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Tutorials:SynchroTrace Sigil IISWC 2016

2016-09-22T21:29:10Z

Scott:

= IEEE International Symposium on Workload Characterization (IISWC), 2016 =
'''September 25-27, Providence, Rhode Island, USA'''

==Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation==

===Organizers===
[http://engineering.tufts.edu/ece/people/hempstead.htm Dr. Mark Hempstead], ''Tufts University''

[[Baris Taskin| Dr. Baris Taskin]], ''Drexel University''

[[Karthik Sangaiah]], ''Drexel University''

[[Michael Lui]], ''Drexel University''

===Topic Outline===

In this tutorial, we discuss the SynchroTrace simulation framework -- a fast trace-driven simulation tool for large design space exploration. The tutorial discusses the two major components of the framework: the trace generation tool, Sigil2, and the architectural simulator, SynchroTraceGen.

===Synopsis===

Current architectures trend towards more cores, including ASIC IPs, general purpose CPUs, and GPUs. Understanding how these cores communicate and interact with each other will be ''critical'' to extracting the most performance and efficiency out of future architectures. The Drexel VLSI & Architecture Lab has developed a set of tools are required to enable this by extracting information on how cores communicate. Our proposed solutions are [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil], a tool to capture platform-independent communication, and [[SynchroTrace]], a framework which extends Sigil and adds mechanisms to enable simulation of future systems.

In this tutorial we discuss the implementation of our tools and also demonstrate the example use-cases.

The [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil] tool is written to capture and classify computation operations, communication edges between functions/threads, and intercept synchronization operations in threads; Sigil data give insight into the true costs that exist within a workload. This enables data-driven design decisions and analysis in designing future systems. We discuss how a Shadow memory implementation of Sigil can capture platform-independent data and also briefly discuss how the data can be applied to perform HW/SW partitioning.

The [[SynchroTrace]] simulation framework utilizes Sigil's platform-independent traces to quickly explore a design space. Synchronization aware traces and replay of those traces, instead of single-threaded deterministic traces, enables accurate simulation of communication bound architectures. With the addition of fast trace-driven simulation, SynchroTrace quickly iterates over a large design space and assists with design decisions such as NoC design and memory models. We discuss the intercept mechanism by which the Sigil tool is able to capture synchronization constructs. We will also discuss and demonstrate SynchroTrace's trace capture and simulation mechanisms in detail.

===Agenda===

# Overview and welcome
# Sigil; a Communication-aware workload profiling tool (''45 minutes'')
## Trace capture
## Running Sigil
## HW/SW partitioning example
## Example on running post-processing
# SynchroTrace (''45 minutes'')
## SynchroTraceGen: a Sigil extension
## SynchroTraceGen trace format
## Generating traces
## SynchroTrace Replay
## Replaying traces
## Results from paper: Speedy, yet accurate simulation
# Hands-on Sigil
## Downloading and installing Sigil
## Running Sigil and interpreting output
## Running post-processing and parsing
# Hands-on SynchroTrace
## Downloading and installing SynchroTrace
## Running Sigil and interpreting trace generation
## Running Replay and understanding Replay output

===Related Media and Links===
[https://github.com/dpac-vlsi SynchroTrace and Sigil Download]

Scott Lerner

2015-11-11T16:41:34Z

Scott:

File:Scott CV v1.pdf

2015-11-11T16:41:15Z

Scott:

News/Events

2015-04-23T15:47:36Z

Scott:

* Scott Lerner received 52nd DAC Richard Newton Young Fellowship from Design Automation Conference in 2015.

* Scott Lerner received the DoD NSDEG fellowship (declined) in 2015.

* Scott Lerner received the NSF GRFP Fellowship in 2015. [http://drexel.edu/fellowships/studentprofiles/profiles/Scott%20Lerner/ Drexel Fellowship Office news]
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File:ScottNSF.png
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* Giordano Salvador received the NSF GRFP Fellowship in 2015.

* Can Sitik and Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2015.

* Prof. Taskin is the TPC chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2015 [http://sliponline.org]

* Scott Lerner received the A. Richard Newton Young Student Fellow Program travel grant from Design Automation Conference in 2014.

* Karthik Sangaiah received the NSF GRFP Fellowship in 2014. [http://drexel.edu/fellowships/studentprofiles/profiles/Karthik%20Sangaiah/ Drexel Fellowship Office news]
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File:PacoNSF.png
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* Can Sitik received the Leroy L. Rosser fellowship from Drexel University in 2014.

* Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2014.

* Best paper nomination for Can Sitik at the ACM GLSVLSI 2013 for the paper entitled [[media:Can_GLSVLSI13.pdf‎|"Skew-Bounded Low Swing Clock Tree Optimization"]].

* Can Sitik received the George Hill, Jr. fellowship from Drexel University in 2013.

* Prof. Taskin is selected the "Young Electrical Engineer of the Year 2013" by the IEEE Philadelphia Section.

* Prof. Taskin organized and presented a tutorial on "Resonant Clocking" with Prof. Matthew Guthaus of UCSC and Drexel VLSI Lab Alumni Dr. Vinayak Honkote of Intel at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012 in San Jose, CA. [http://iccad.com/2012_event_details?id=149-10-D program link]

* Drexel student newspaper article on hybrid wireless NoC project [http://thetriangle.org/2012/08/31/antennas-allow-microchips-to-go-wireless/ Drexel Triangle link]
* News release from Drexel about our hybrid wireless NoC project [http://www.drexel.edu/now/news-media/releases/archive/2012/August/Wireless-Network-on-Chip/ August 2012 DrexelNOW link]
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File:Chip_CourtesyBarisTaskin-300x225.jpg
File:microchip.jpg
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* Dr. Taskin received the ACM SIGDA Distinguished Service Award in 2012.

* Ying Teng received the George Hill, Jr. fellowship from Drexel University in 2012.

* See our article titled [[WirelessInterconnect|"What is Wireless Interconnect?"]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.

* Ying Teng received the N. Bilgutay fellowship from the Department of Electrical & Computer Engineering, Drexel University in 2011.

* Here is the report for the Drexel Office of International Programs travel award for Dr. Taskin to ISCAS'11. [http://www.drexel.edu/international/assets/pdf/ita/faculty/2011-Taskin_Baris.pdf]
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File:Facultyspotlight.png
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* Ying Teng's first journal paper "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect" is featured on the cover of the Journal of Low Power Electronics (JOLPE) in December 2010. Check out the [[Publications]] page for details.
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* Ankit More received the George Hill, Jr. fellowship from Drexel University in 2010.

* Jianchao Lu and Ying Teng presented their work in University Booth, at the ACM/IEEE Design Automation Conference in Anaheim, CA, in 2010.
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File:Jianchao_2010_dac.JPG
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* Sharat Chandra recipient of the Young Student Support Program Award for the Design Automation Conference in Anaheim, CA in 2010:
[http://www.sigda.org/youngstudent.html Young Student Support Program DAC]

* The NSF-funded REU Site opportunity on "Computing for Power and Energy" directed by Dr. Taskin is starting in Summer 2010: [http://reu.ece.drexel.edu REU Site on Computing for Power and Energy: The Old, The New and The Renewable]. This site will run for the next three years.
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* Vinayak received the first N. Bilgutay fellowship from the Department of Electrical & Computer Engineering, Drexel University in 2010.

* Jianchao Lu and Vinayak Honkote presented their work in University Booth and Ph.D. Forum, respectively, at the ACM/IEEE Design Automation Conference in San Francisco, CA, in 2009.
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File:dac2009_jianchao.jpg
File:dac2009_vinayak.jpg
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* Jianchao Lu and Vinayak Honkote participated in the SIGDA CADAthlon at ICCAD 2008 in San Jose, CA.
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* Accepting the ''A. Richard Newton Award'' at the ACM/IEEE Design Automation Conference in 2007.
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* Drexel Senior Design team, also winners of the CE award, presented at the University Booth at the ACM/IEEE Design Automation Conference in San Diego, CA, in 2007.
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News/Events

2015-04-23T15:47:26Z

Scott:

Scott Lerner

2015-04-17T12:49:22Z

Scott:

File:Scott CV cp.pdf

2015-04-17T12:43:34Z

Scott: uploaded a new version of "File:Scott CV cp.pdf"

SynchroTrace

2015-04-07T15:51:46Z

Scott:

<anyweb> http://dpac.ece.drexel.edu/current-research-projects/synchrotrace/ </anyweb>

The above page is embedded from Prof. Mark Hempstead's webpage

== SynchroTrace ==

SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of CMPs. The first step, capturing synchronization-aware traces of multi-threaded applications, leverages an extension of prior work (Sigil). The second step represents an timing model for replaying the synchronization-aware traces into external architecture models. Together, these two stages represent ‘SynchroTrace’.

To leverage this methodology for design space exploration, we have developed a prototype of SynchroTrace integrated into the cache and NoC simulators of Gem5 (Ruby and Garnet, respectively). We defined this prototype integration as the SynchroTrace Simulation Framework, and the code for this framework is available below.

=Overview:=

The capture tool is built from Sigil, which leverages the Valgrind dynamic binary instrumentation tool. The processed instructions from the native multi-threaded applications are abstracted into (3) events: Computation (Work performed local to a thread), Communication (Read/Write dependencies between threads), and Synchronization (embedded pthread calls for each thread). These events form a trace for each individual thread, so that these threads may progress in parallel when replaying the traces.

Computation Event (indicated by the $ and * symbols):
[Thread ID, Event Number, Number of Integer Operations, Number of Floating Point Operations, Number of Memory Reads, Number of Memory Writes $ Range of Unique Addresses Written * Range of Unique Addresses Read]

Communication Event (indicated by the # symbol):
[Thread ID, Event Number # Producer Thread ID, Produce Event Number, Range of Unique Addresses Read]

Synchronization Event (indicated by the pth_th and ^ symbol):
[Thread ID, Event Number, pth_ty: Pthread Call Type ^ Address of Synchronization Structure]

=Replay Model:=

Traces are fed into the replay timing model, which acts as an interface into the external architecture models.

[[File:replay_diagram.jpg|600px| SynchroTrace Replay]]

replay_diagram

The Replay portion of SynchroTrace is comprised of 4 entities:

Trace Translator – Converts the traces into an event form to be fed into the timing model.

Event Queue Manager – Centralized event queue that manages the timing of thread progression based on the three types of events. The Event Queue Manager also handles the timing for when to send memory requests to the external cache simulator.

Thread Scheduler – Creates and maintains the thread state. The Thread Scheduler includes a light-weight swapping mechanism to allow for multiple threads to run on a core. The scheduler also handles the appropriate synchronization actions.

Memory Request Manager – Interface to the external architecture models. For the SynchroTrace Simulation Framework, the memory request manager packages the memory requests into requests for Ruby.

=Getting SynchroTrace:=

The SynchroTrace Simulation Framework is accessible through GitHub at: https://github.com/dpac-vlsi

Currently, there is only a repository for playing the synchronization-aware traces into the external cache and NoC models (Ruby and Garnet). We’ve included a few sample traces to test and explore this code-base. We are currently prepping the capture tool for release very soon.

The SynchroTrace publication can be found [[media:SynchroTrace.pdf‎|here]].

= Dependencies:=

The SynchroTrace Simulation Framework is integrated into Gem5′s cache and NoC simulators (Ruby and Garnet). Thus, SynchroTrace’s dependencies are based on Gem5′s dependencies. Please refer to http://www.gem5.org/Dependencies for more information.

SynchroTrace has been tested on Intel Xeon E5-based machines, running either RedHat Enterprise Linux 5, Centos 6, or Ubuntu 12.x operating systems. We have generated traces for PARSEC and Splash-2 benchmarks (up to 64 threads reliably) and ran them through our SynchroTrace Simulation Framework.

= Running the first time:=

Please follow the included Readme to compile SynchroTrace and run the sample traces for the first time.

SynchroTrace

2014-10-31T16:02:25Z

Scott:

== Education ==
'''PhD in Electrical Engineering expected graduation 2018''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Electrical Engineering, 2014''' 
:Drexel University, Philadelphia, PA.
'''B.S. in Computer Engineering, 2014''' 
:Drexel University, Philadelphia, PA.

== Research Interests ==
* Physical Design including Floorplanning, Placement and Routing
* Interconnect Modeling
* Low-swing Clock Tree Topologies

== Curriculum Vitae ==
[[media:Scott_CV_dropbox.pdf‎ | Scott Lerner CV (Feb 2014)]]

== Poster Presentations ==
# S. Lerner, V. Pano, and B. Taskin, Wireless Network-on-Chip, Poster to be presented at Mid-Atlantic ASEE, November 2014
# S. Lerner, Arduino Robotics in the Classroom, Poster to be presented at Mid-Atlantic ASEE, November 2014
# Scott Lerner, and Baris Taskin, Low-Power Clock Network Designs, Poster presented at IEEE Design Automation Conference, June 2014
# S. Lerner, C. Sitik, and B. Taskin, Low Swing Clocking Algorithm for 20nm FinFET Technology, Poster presented at Upsilon Pi Epsilon Research Reception, February 2014.
# S. Lerner, C. Sitik, and B. Taskin, Sub-45nm Interconnect Modeling, Poster presented at Drexel IEEE Graduate Forum, February 2014.
# S. Lerner, R. Welliver, B. Derveni, C. Schoenfield, I. Yilmaz, MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, presented at Philly Codefest, February 2014.
# C. Sitik, S. Lerner, and B. Taskin, Low-Power/High-Performance Clock Network Design for Microprocessors, Poster presented at Upsilon Pi Epsilon Research Reception, February 2013.

== Selected Publications ==
# S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015.
# C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014.

== Awards ==
# NSF Research Experience for Undergraduate (REU) Grant 2014
# A. Richard Newton Young Fellow Award 2014
# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
# Doctor Thomas Moore Endowed Grant 2014
# Dean's List, 2009, 2010, 2011, 2012, 2013, 2014

== Selected Projects ==
# Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
Department of ECE 
Drexel University 
Bossone 324 
Philadelphia 
Pennsylvania 19104 

'''Phone:''' (863) 307-6194 
'''Fax:''' (215) 895-1695 
'''Email: '''spl29@drexel.edu