https://research.coe.drexel.edu/ece/vlsi/api.php?action=feedcontributions&feedformat=atom&user=Taskin 2026-05-12T22:52:16Z User contributions MediaWiki 1.39.3 https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=8390 2026-02-03T14:36:32Z

<p>Taskin: /* Collaborators */</p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> <br /> Prof Amlan Ganguly (RIT)<br /> <br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkiye)<br /> <br /> Junghoon Oh Ph.D. (visiting PhD student co-author on research products, Japan Institute of Technology, advised by Prof. Mineo Kaneko)<br /> <br /> Vinayak Honkote, Ph.D., Ragh Kuttappa, Intel, OR (co-authors on research products)<br /> <br /> == Publications ==<br /> Publications list is updated 2026/01. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * Kyei Anim, Baris Taskin, Amlan Ganguly and~Kapil~Dandekar, &quot;Reconfigurable Through-Silicon-Via Waveguides for 2.5D IC Wireless Interconnects” (in review)<br /> <br /> * Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025 DOI:10.1145/3716368.3735247.<br /> <br /> * Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, Proceedings of the IEEE Design Automation and Test In Europe (DATE), March 2025. DOI:10.23919/DATE64628.2025.10993124<br /> <br /> * Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD), November 2024. DOI:10.1145/3676536.3676720<br /> <br /> * Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Undergraduate summer research, STAR freshman program, Jonah Taylor<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 1/2026</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=8389 2026-02-03T14:35:36Z

<p>Taskin: </p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkiye)<br /> <br /> Junghoon Oh Ph.D. (visiting PhD student co-author on research products, Japan Institute of Technology, advised by Prof. Mineo Kaneko)<br /> <br /> Vinayak Honkote, Ph.D., Ragh Kuttappa, Intel, OR (co-authors on research products)<br /> <br /> == Publications ==<br /> Publications list is updated 2026/01. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * Kyei Anim, Baris Taskin, Amlan Ganguly and~Kapil~Dandekar, &quot;Reconfigurable Through-Silicon-Via Waveguides for 2.5D IC Wireless Interconnects” (in review)<br /> <br /> * Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025 DOI:10.1145/3716368.3735247.<br /> <br /> * Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, Proceedings of the IEEE Design Automation and Test In Europe (DATE), March 2025. DOI:10.23919/DATE64628.2025.10993124<br /> <br /> * Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD), November 2024. DOI:10.1145/3676536.3676720<br /> <br /> * Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Undergraduate summer research, STAR freshman program, Jonah Taylor<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 1/2026</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=8388 2026-02-03T14:31:15Z

<p>Taskin: /* Publications */</p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkiye)<br /> <br /> Junghoon Oh Ph.D. (visiting PhD student co-author on research products, Japan Institute of Technology, advised by Prof. Mineo Kaneko)<br /> <br /> Vinayak Honkote, Ph.D., Ragh Kuttappa, Intel, OR (co-authors on research products)<br /> <br /> == Publications ==<br /> Publications list is updated 2026/01. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * Kyei Anim, Baris Taskin, Amlan Ganguly and~Kapil~Dandekar, &quot;Reconfigurable Through-Silicon-Via Waveguides for 2.5D IC Wireless Interconnects” (in review)<br /> <br /> * Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025 DOI:10.1145/3716368.3735247.<br /> <br /> * Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, Proceedings of the IEEE Design Automation and Test In Europe (DATE), March 2025. DOI:10.23919/DATE64628.2025.10993124<br /> <br /> * Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD), November 2024. DOI:10.1145/3676536.3676720<br /> <br /> * Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Undergraduate summer research, STAR freshman program, Jonah Taylor<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 10/2024</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=8387 2025-09-30T15:04:49Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> # Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025 [https://doi.org/10.1145/3716368.3735247 DOI:10.1145/3716368.3735247].<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025. [https://doi.org/10.23919/DATE64628.2025.10993124 DOI:10.23919/DATE64628.2025.10993124] [https://arxiv.org/abs/2504.11376 Arxiv]<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://doi.org/10.1145/3676536.3676720 DOI:10.1145/3676536.3676720][https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=8386 2025-09-30T15:04:01Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> # Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025. [https://doi.org/10.23919/DATE64628.2025.10993124 DOI:10.23919/DATE64628.2025.10993124] [https://arxiv.org/abs/2504.11376 Arxiv]<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://doi.org/10.1145/3676536.3676720 DOI:10.1145/3676536.3676720][https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=8385 2025-09-30T15:02:23Z

<p>Taskin: </p> <hr /> <div>== Conferences ==<br /> # Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025. [https://doi.org/10.23919/DATE64628.2025.10993124 DOI:10.23919/DATE64628.2025.10993124] [https://arxiv.org/abs/2504.11376 Arxiv]<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=8384 2025-09-30T15:01:23Z

<p>Taskin: </p> <hr /> <div>== Conferences ==<br /> # Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025. [https://doi.org/10.23919/DATE64628.2025.10993124. DOI:10.23919/DATE64628.2025.10993124] [https://arxiv.org/abs/2504.11376 Arxiv]<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=8383 2025-09-30T15:00:36Z

<p>Taskin: </p> <hr /> <div>== Conferences ==<br /> # Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025. [DOI: 10.23919/DATE64628.2025.10993124 ACM] [https://arxiv.org/abs/2504.11376 Arxiv]<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=8382 2025-09-05T18:12:16Z

<p>Taskin: </p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> #''Unconventional Computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.<br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> &lt;!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage.--&gt; <br /> &lt;!--# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.--&gt;<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=8381 2025-09-05T18:11:38Z

<p>Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */</p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> #''Unconventional Computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.<br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> #''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. <br /> &lt;!--# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.--&gt;<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Ceyhun Kayan]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=8377 2025-05-23T16:48:59Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> # Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025. [https://arxiv.org/abs/2504.11376 Arxiv]<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=8376 2025-05-23T16:26:29Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> # Yilmaz Ege Gonul, Ceyhun Efe Kayan, Ilknur Mustafazade, Nagarajan Kandasamy and Baris Taskin, &quot;GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)&quot;, June 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=7731 2025-02-05T19:47:35Z

<p>Taskin: </p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> #''Unconventional Computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.<br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> &lt;!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. --&gt;<br /> # ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Ceyhun Kayan]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Taskin_CV.pdf&diff=7730 2025-02-05T19:47:03Z

<p>Taskin: Taskin uploaded a new version of File:Taskin CV.pdf</p> <hr /> <div></div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=7729 2025-02-05T19:46:21Z

<p>Taskin: /* Curriculum Vitae */</p> <hr /> <div>&lt;!-- [[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin's quintessential professor's outdated photo 2005]]|25px]] --&gt;<br /> [[File:BarisTaskin05small.jpg|right|border|frame|[[2023 photo]]|x1px]]<br /> <br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering Department at Drexel University, Philadelphia, PA in 2005, where currently he is a Professor. Between 2003-2004, he was a PhD intern engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015. He is an associate editor for JCSC and Elsevier's Microelectronics. He served as the General Chair for SLIP 2016 and GLVLSI 2019, as the Chair for IEEE CEDA Pennsylvania Chapter (2018-current), and the Chair of the IEEE Circuits and Systems Society's VLSI and Systems Applications Technical Committee (IEEE CASS VSA-TC) (2018-2020).<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Professor (2016-present)<br /> ; Associate Professor (2011-2016)<br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Ph.D. Intern Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> &lt;!-- [http://vlsi.ece.drexel.edu/images/8/81/Taskin_CV.pdf CV (September 2024)] --&gt;<br /> <br /> [http://vlsi.ece.drexel.edu/images/8/81/Taskin_CV.pdf CV (February 2025)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> '''Campus Location:'''<br /> &lt;br&gt; Office: Bossone Building 401<br /> &lt;br&gt; Lab: Bossone Building 405<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7728 2025-02-05T15:44:28Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://research.coe.drexel.edu/ece/vlsi/images/6/6d/Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7727 2025-02-05T15:44:06Z

<p>Taskin: </p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [https://research.coe.drexel.edu/ece/vlsi/index.php/File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf PRE-PRINT]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7726 2025-02-05T15:43:08Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [[https://research.coe.drexel.edu/ece/vlsi/index.php/File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf|PRE-PRINT]]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7725 2025-02-05T15:41:43Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [[:File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf|PRE-PRINT]]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7724 2025-02-05T15:40:56Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [[:File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf|PAPER]]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7723 2025-02-05T15:40:23Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe (DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [[File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf|PAPER]]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7722 2025-02-05T15:40:06Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe~(DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [[File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf|PAPER]]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558659. [https://ieeexplore.ieee.org/document/10558659 PAPER]<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf&diff=7721 2025-02-05T15:37:07Z

<p>Taskin: </p> <hr /> <div></div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7720 2025-02-05T15:36:30Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe~(DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [[File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf|PAPER]]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7719 2025-02-05T15:36:14Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe~(DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024. [[File:Multi_Phase_Coupled_CMOS_Ring_Oscillator_based_Potts_Machine.pdf|pdf]]<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7718 2025-02-05T15:32:52Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe~(DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024.<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10558674.[https://ieeexplore.ieee.org/document/10558674 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7717 2025-02-05T15:31:16Z

<p>Taskin: /* Conferences */</p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe~(DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024.<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022, pp. 692-696, doi: 10.1109/ISCAS48785.2022.9937877. [https://ieeexplore.ieee.org/document/9937877 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Publications&diff=7716 2025-02-05T15:24:38Z

<p>Taskin: </p> <hr /> <div>== Conferences ==<br /> #Yilmaz Gonul, Baris Taskin, &quot;A Multi-Stage Potts Machine based on Coupled CMOS Ring Oscillators&quot;, ''Proceedings of the IEEE Design Automation and Test In Europe~(DATE)'', March 2025.<br /> #Yilmaz Gonul, Baris Taskin, &quot;Multi-phase Coupled CMOS Ring Oscillator based Potts Machine&quot;, ''Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD)'', November 2024.<br /> #Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2024.<br /> #Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, and Anuradha Srinivasan, &quot;Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa and Baris Taskin, &quot;A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2022.<br /> #Ragh Kuttappa, Leo Fiippini, Nicholas Sica and Baris Taskin, &quot;Scalable Resonant Power Clock Generation for Adiabatic Logic Design&quot;, ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021, pp. 338--342. [https://ieeexplore.ieee.org/document/9516795 PAPER]<br /> #Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;FinFET -- Based Low Swing Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181175 PAPER]<br /> #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, &quot;SnackNoc: Processing in the Communication Layer&quot;, ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020. [https://ieeexplore.ieee.org/document/9065591 PAPER]<br /> #Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> #Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, &quot;Robust Low Power Clock Synchronization for Multi-Die Systems&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]<br /> #Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, &quot;Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]<br /> #Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Low Voltage Clock Tree Synthesis with Local Gate Clusters&quot;, ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]<br /> #Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> #Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, &quot;Low Swing -- Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.<br /> #Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> #Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> #Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> #Ragh Kuttappa and Baris Taskin, &quot;Low Frequency Rotary Traveling Wave Oscillators&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]<br /> #Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, &quot;Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces&quot;, ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]<br /> #Leo Filippini, Lunal Khuon, and Baris Taskin, &quot;Charge Recovery Implementation of an Analog Comparator: Initial Results&quot;, in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]<br /> #Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, &quot;Wireless NoCs using Directional and Substrate Propagation Antennas&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;A Charge Recovery Logic System Bus&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]<br /> #Scott Lerner, Eric Leggett and Baris Taskin, &quot;Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]<br /> #Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, &quot;Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]<br /> #Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, &quot;Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]<br /> #Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, &quot;Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, &quot;Energy Aware Routing of Multi-Level Network-on-Chip Traffic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]<br /> #Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, &quot;Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]<br /> #Leo Filippini and Baris Taskin, &quot;Charge Recovery Logic for Thermal Harvesting Applications&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]<br /> # Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]<br /> #Karthik Sangaiah, Mark Hempstead and Baris Taskin, &quot;Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling&quot;, ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]<br /> #Leo Filippini, Emre Salman, Baris Taskin, &quot;A Wirelessly Powered System with Charge Recovery Logic&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, &quot;Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies&quot;, to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]<br /> #Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, &quot;A Novel Static D Flip-Flop Topology for Low Swing Clocking&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]<br /> #Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, &quot;Enhanced Level Shifter for Multi-Voltage Operation&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]<br /> #Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, &quot;Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication&quot;, ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]<br /> #[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]<br /> #Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, &quot;Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]<br /> #Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, &quot;Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation&quot;, ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Frequency-Centric Resonant Rotary Clock Distribution Network Design&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]<br /> # Can Sitik, Scott Lerner and Baris Taskin, &quot;Timing Characterization of Clock Buffers for Clock Tree Synthesis&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]<br /> # Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead &quot;Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]<br /> #Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, &quot;High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]<br /> #Julian Kemmerer and Baris Taskin, &quot;Range-based Dynamic Routing of Hierarchical On Chip Network Traffic&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)&quot;, June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]<br /> #Ying Teng and Baris Taskin, &quot;Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]<br /> # Can Sitik, Prawat Nagvajara and Baris Taskin, &quot;A Microcontroller-Based Embedded System Design Course with PSoC3&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Corner Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies&quot;, ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler&quot;, ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.<br /> # Ying Teng and Baris Taskin, &quot;Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]<br /> # Matthew Guthaus and Baris Taskin, &quot;High-Performance, Low-Power Resonant Clocking: Embedded tutorial&quot;, ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Multi-Voltage Domain Clock Mesh Design&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;Synchronization Scheme for Brick-Based Rotary Oscillator Arrays&quot;, ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]<br /> # Ankit More and Baris Taskin, &quot;A Unified Design Methodology for a Hybrid Wireless 2-D NoC&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]<br /> # Vinayak Honkote, Ankit More and Baris Taskin, &quot;3-D Parasitic Modeling for Rotary Interconnects&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]<br /> # Ankit More and Baris Taskin, &quot;EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]<br /> # Ying Teng, Jianchao Lu and Baris Taskin, &quot;ROA-Brick Topology for Rotary Resonant Clocks&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC&quot;, ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program&quot;, ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]<br /> # Jianchao Lu, Yusuf Aksehir and Baris Taskin, &quot;Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]<br /> &lt;!-- # Sharat Shekar and Michael Bowen, &quot;Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX&quot;, ''Proceedings of Synopsys User Guide Conference San Jose (SNUG)'', March 2011. --&gt;<br /> # Ying Teng and Baris Taskin, &quot;Process Variation Sensitivity of the Rotary Traveling Wave Oscillator&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]<br /> # Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, &quot;Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing&quot;, ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]<br /> &lt;!-- # Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, &quot;Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.--&gt;<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Wireless Interconnects for Inter-tier Communication on 3-D ICs&quot;, ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC&quot;, ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits&quot;, ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings&quot;, ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Compatibility of CMOS On-chip Antennas&quot;, ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Tree Synthesis with XOR Gates for Polarity Assignment&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation and Analysis of Resonant Rotary Clocking Technology&quot;, ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation&quot;, ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects&quot;, ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Leakage Current Analysis for Intra-Chip Wireless Interconnects&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment Considering Capacitive Load&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array&quot;, ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Incremental Register Placement for Low Power CTS&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking&quot;, ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Clock Skew Scheduling with Limited Delay Buffering&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies&quot;,'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Zero Clock Skew Synchronization with Rotary Clocking Technology&quot;, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Custom Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]<br /> # Baris Taskin and Jianchao Lu, &quot;Post-CTS Delay Insertion to Fix Timing Violations&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]<br /> # Shannon Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of Nonzero Clock Skew Circuits&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;Maze Router Based Scheme for Rotary Clock Router&quot;, ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]<br /> # Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Prawat Nagvajara and Baris Taskin, &quot;Design-for-Debug: A Vital Aspect in Education&quot;, ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]<br /> #Baris Taskin and Ivan S. Kourtev, &quot;A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]<br /> # Baris Taskin, John Wood and Ivan S. Kourtev, &quot;Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking&quot;, ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Dual-Phase Line-Based QCA Memory Design&quot;, ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Improvement of Edge-Triggered Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Advanced Timing of Level-Sensitive Sequential Circuits&quot;, ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew&quot;, ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches&quot;, ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]<br /> <br /> == Journals ==<br /> # A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> # Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, &quot;Multiphase Digital Low-Dropout Regulators&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 30, No. 1, pp. 40--50, January 2022. [https://ieeexplore.ieee.org/document/9560724 PAPER]<br /> # Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> # Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', Vol. 10. No. 1, pp. 100-113, March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> # Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', February 2020. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> # Ragh Kuttappa, Selcuk Kose, and Baris Taskin, &quot;FOPAC: Flexible On-Chip Power and Clock&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]<br /> # Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> # Leo Filippini and Baris Taskin, &quot;The adiabatically driven strongarm comparator&quot;, ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]<br /> # Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, &quot;RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]<br /> # Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, &quot;SLECTS: Slew-Driven Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]<br /> #Scott Lerner, Isikcan Yilmaz, and Baris Taskin, &quot;Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]<br /> #Scott Lerner and Baris Taskin, &quot;Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]<br /> #Ankit More, Vasil Pano, and Baris Taskin, &quot;Vertical Arbitration-free 3D NoCs&quot;, ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]<br /> #K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, &quot;SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads&quot;, ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]<br /> # Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, &quot;Design Methodology for Voltage-Scaled Clock Distribution Networks&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]<br /> # Ankit More and Baris Taskin, &quot;Locality-Aware Network Utilization Balancing in NoCs&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]<br /> # Ying Teng and Baris Taskin, &quot;ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]<br /> # Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, &quot;FinFET-Based Low Swing Clocking&quot;, ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]<br /> # Can Sitik and Baris Taskin, &quot;Iterative Skew Minimization for Low Swing Clocks&quot;, ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;ZeROA: Zero Clock Skew Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]<br /> # Jianchao Lu, Ying Teng and Baris Taskin, &quot;A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]<br /> # Jianchao Lu, Xiaomi Mao and Baris Taskin, &quot;Integrated Clock Mesh Synthesis with Incremental Register Placement&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER] <br /> # Jianchao Lu and Baris Taskin, &quot;Clock Buffer Polarity Assignment with Skew Tuning&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]<br /> # Vinayak Honkote and Baris Taskin, &quot;CROA: Design and Analysis of Custom Rotary Oscillatory Array&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]<br /> # Shannon M. Kurtas and Baris Taskin, &quot;Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling&quot;, ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]<br /> # Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, &quot;Design of an Addressable Internetworked Microscale Sensor&quot;, ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]<br /> # [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot;, ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]<br /> # Jianchao Lu and Baris Taskin, &quot;Post-CTS Delay Insertion&quot;, ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit&quot;, ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]<br /> # Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, &quot;Custom Topology Rotary Clock Router&quot;, ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]<br /> # Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, &quot;A Shift-Register Based QCA Memory Architecture&quot;, ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]<br /> # Baris Taskin and Bo Hong, &quot;Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Delay Insertion Method in Clock Skew Scheduling&quot;, ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]<br /> # Baris Taskin and Ivan S. Kourtev, &quot;Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits&quot;, ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]<br /> <br /> == Books and Book Chapters ==<br /> <br /> # Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.<br /> # Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.<br /> <br /> <br /> &lt;gallery&gt;<br /> File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&amp;+systems/book/978-0-387-71055-6]<br /> File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]<br /> &lt;/gallery&gt;<br /> <br /> <br /> &lt;!--<br /> == Tutorials ==<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2016|Sigil2 and SynchroTrace: Platform Independent Workload Profiling and Fast Memory-NoC Simulation]] @ IEEE International Symposium on Workload Characterization (IISWC), 2016, Providence, RI (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil ICCD 2015|Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation]] @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * [[Tutorials:SynchroTrace Sigil IISWC 2015|Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace]] @ IEEE International Symposium on Workload Characterization (IISWC), 2015, Atlanta, GA (with Prof. Mark Hempstead, Tufts University).<br /> <br /> * Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015, Lisbon, Portugal (with Prof. Emre Salman, Stony Brook University).<br /> <br /> * High Performance, Low Power Resonant Clocking @ ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2012, San Jose, CA (with Prof. Matthew Guthaus, UCSC).<br /> <br /> --&gt;<br /> <br /> == Thesis and Dissertations ==<br /> <br /> * Scott Lerner, Ph.D. Dissertation: &quot;Bounded and Variation-aware Design for Clock Tree Synthesis&quot;, 2024<br /> <br /> * Ragh Kuttappa, Ph.D. Dissertation: &quot;Scalable and Shareable Resonant Rotary Clocks&quot;, 2021<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Karthik Sangaiah, Ph.D. Dissertation: &quot;Reimagining the Role of Network-on-Chip Resources Toward Improving Chip Multiprocessor Performance&quot;, 2020<br /> <br /> * Steven Khoa, M.S. Thesis, ''[Adiabatic Step Charging Power Clock Generator]'', 2020<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> * Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019<br /> <br /> * A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015<br /> <br /> * Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014 <br /> <br /> * Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013<br /> <br /> * Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011<br /> <br /> * Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010<br /> <br /> * Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=News/Events&diff=7715 2025-02-05T15:22:19Z

<p>Taskin: </p> <hr /> <div><br /> * Scott is now Dr. Scott Lerner, Summer 2024.<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2023-2024.<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Fall 2023-2024.<br /> <br /> <br /> * Yilmaz Gonul participated in DAC Young Fellows program at DAC 2023. <br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2022-2023.<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Winter 2022-2023.<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2021-2022.<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Winter 2020.<br /> <br /> <br /> * Dr. Taskin is delivering the keynote &quot;On-Chip Wireless Interconnect Paradigm&quot; at [http://www.nocarc.org 12th International Workshop on Network on Chip Architectures (NoCARC) 2019], held in conjuction with MICRO 2019 in Columbus Ohio.<br /> &lt;gallery&gt;<br /> File:NoCARC19Keynote.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Mike Lui is interning at Facebook Fall 2019.<br /> <br /> <br /> * Scott Lerner is interning at Intel Summer/Fall 2019. <br /> <br /> <br /> * Vasil is now Dr. Vasil Pano, Summer 2019.<br /> <br /> <br /> * Leo is now Dr. Leo Filippini, Spring 2019.<br /> <br /> <br /> * Our resonant clock team RotaSyn participated in National Science Foundation I-Corps Short Course at Drexel University organized by Upstate NY I-Corps Node, March 2019.<br /> &lt;gallery&gt;<br /> File:Rotasyn-Session5Cover.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is On for Winter 2019.<br /> <br /> <br /> * Scott Lerner received the Koerner Family Award in 2019.<br /> <br /> <br /> * Dr. Taskin is the General Chair for ACM GLSVLSI 2019 in Tysons Corner, VA.<br /> &lt;gallery&gt;<br /> File:GLSVLSI19Chair.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> * Dr. Taskin elected the chair of [http://ieee-cas.org/community/technical-committees/vlsi-systems-applications-technical-committee-vsatc IEEE Circuits and Systems Society's (CASS) Technical Committee on VLSI Systems and Applications (CAS VSA-TC)], 2018-2020.<br /> &lt;gallery&gt;<br /> File:VSATCChair.png<br /> &lt;/gallery&gt;<br /> <br /> * Vasil Pano received the Nihat Bilgutay Award in 2018.<br /> <br /> <br /> * Mike Lui received the Koerner Family Award in 2018. <br /> <br /> <br /> * Karthik Sangaiah, Scott Lerner, and Ragh Kuttappa receive the Weggel Family Fellowship in 2018.<br /> <br /> <br /> * Scott Lerner, Vasil Pano and Baris Taskin won the first place at the 10th Annual Drexel IEEE Graduate Symposium poster competition for their work on &quot;NoC Router Lifetime Improvement Using Per-Port Router Utilization&quot;, accepted at IEEE International Symposium on Circuits and Systems (ISCAS).<br /> <br /> <br /> * Completed CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2018.<br /> <br /> <br /> * Dr. Taskin is the TPC co-chair for ACM GLSVLSI 2018 in Chicago, IL.<br /> <br /> <br /> * Granted United States Patent No. 9,773,079, ``Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits'', Inventors: Taskin and Sitik, 2017<br /> <br /> <br /> *Granted United States Patent No. 9,484,896, ``Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling'', Inventors: Taskin and Teng, 2017<br /> <br /> <br /> * Scott Lerner, Vasil Pano, and Leo Filippini receive ECE awards in 2017.<br /> <br /> <br /> * Mike Lui and Kartik Sangaiah will give a tutorial on &quot;Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation&quot; @ International Symposium on Workload Characterization (IISWC), 2016.<br /> <br /> <br /> * Can Sitik received Honorable mention for the Outstanding Dissertation Award at Drexel College of Engineering graduation in 2016.<br /> <br /> <br /> * Scott received the Frank &amp; Agnes Seaman fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2016.<br /> <br /> <br /> * Leo received the Carleone fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2016.<br /> <br /> <br /> * Vasil Pano and Scott Lerner recipients of the A. Richard Newton Young Student Fellow Program award for the Design Automation Conference in Austin, TX in 2016.<br /> <br /> <br /> * Junghoon Oh, a PhD student from JAIST, Japan, joins the lab as a visiting researcher for 2016.<br /> <br /> <br /> * IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Spring 2016.<br /> &lt;gallery&gt;<br /> File:2016_Sp_symposiaFlyer.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * The first IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium talk for Spring 2016.<br /> &lt;gallery&gt;<br /> File:2016_Sp_symposium_01.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2016.<br /> &lt;gallery&gt;<br /> File:symposia-winterFlyer16.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Prof. Taskin is the General Chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016 [http://sliponline.org]<br /> <br /> <br /> * Dr. Taskin received the Outstanding Research award from the Drexel ECE Department in 2015.<br /> <br /> <br /> * Dr. Taskin started and will serve as the treasurer of the IEEE Central Pennsylvania, Pittsburgh, Philadelphia Joint Sections Council of Electronic Design Automation (CEDA) Chapter.<br /> <br /> <br /> * Tutorial delivered at ICCD 2015: &quot;Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation&quot; @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University, Stephan Diestelhorst, ARM Research).<br /> <br /> <br /> * Drexel Computer Engineering Graduate Symposium program for Fall, Winter and Spring 2015.<br /> &lt;gallery&gt;<br /> File:symposia-fallFlyer15.png<br /> File:symposia-winterFlyer15.png<br /> File:symposia-springFlyer15.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Two familiar faces on the cover of the 2014-15 report from the Drexel Fellowship Office; Paco as a mentor (GRFP 2014) and Scott for having received the NDSEG and GRFP this year in 2015. [http://www.drexel.edu/fellowships/about/overview/Annual%20Report/ Drexel Fellowship Office 2014-2015 Report]<br /> <br /> <br /> * Mike Lui will give a tutorial on &quot;Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace&quot; @ International Symposium on Workload Characterization (IISWC), 2015.<br /> &lt;gallery&gt;<br /> File:IISWC_flyer.png<br /> &lt;/gallery&gt;<br /> <br /> * Dr. Taskin and [http://nanocas.ece.stonybrook.edu/salman/ Dr. Salman (Stony Brook University)] gave a tutorial on &quot;Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances&quot; @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015 in Lisbon, Portugal [http://www.iscas2015.org/program/tutorials/].<br /> <br /> <br /> * Renamed &quot;Drexel VLSI Lab&quot; to &quot;Drexel VLSI and Architecture Lab&quot; to more accurately reflect the current [[Research]] portfolio.<br /> <br /> <br /> * Scott Lerner received 52nd DAC Richard Newton Young Fellowship from Design Automation Conference in 2015.<br /> <br /> <br /> * Scott Lerner received the DoD NSDEG fellowship (declined) in 2015.<br /> <br /> <br /> * Scott Lerner received the NSF GRFP Fellowship in 2015. [http://drexel.edu/fellowships/studentprofiles/profiles/Scott%20Lerner/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:ScottNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Giordano Salvador (REU 2013, REU 2014, also independent research, UPenn) received the NSF GRFP Fellowship in 2015, will attend UIUC.<br /> <br /> <br /> * Michael Miller (REU 2013, Goshen College) received the NSF GRFP Fellowship in 2015, will attend CMU.<br /> <br /> <br /> * Can Sitik and Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2015.<br /> <br /> <br /> * Prof. Taskin is the TPC chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2015 [http://sliponline.org]<br /> <br /> <br /> * Scott Lerner received the A. Richard Newton Young Student Fellow Program travel grant from Design Automation Conference in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the NSF GRFP Fellowship in 2014. [http://drexel.edu/fellowships/studentprofiles/profiles/Karthik%20Sangaiah/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:PacoNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Can Sitik received the Leroy L. Rosser fellowship from Drexel University in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2014.<br /> <br /> <br /> * Best paper nomination for Can Sitik at the ACM GLSVLSI 2013 for the paper entitled [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]].<br /> <br /> <br /> * Can Sitik received the George Hill, Jr. fellowship from Drexel University in 2013.<br /> <br /> <br /> * Prof. Taskin is selected the &quot;Young Electrical Engineer of the Year 2013&quot; by the IEEE Philadelphia Section.<br /> <br /> <br /> * Prof. Taskin organized and presented a tutorial on &quot;Resonant Clocking&quot; with Prof. Matthew Guthaus of UCSC and Drexel VLSI Lab Alumni Dr. Vinayak Honkote of Intel at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012 in San Jose, CA. [http://iccad.com/2012_event_details?id=149-10-D program link]<br /> <br /> <br /> * Drexel student newspaper article on hybrid wireless NoC project [http://thetriangle.org/2012/08/31/antennas-allow-microchips-to-go-wireless/ Drexel Triangle link]<br /> * News release from Drexel about our hybrid wireless NoC project [http://www.drexel.edu/now/news-media/releases/archive/2012/August/Wireless-Network-on-Chip/ August 2012 DrexelNOW link] <br /> &lt;gallery&gt;<br /> File:Chip_CourtesyBarisTaskin-300x225.jpg<br /> File:microchip.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Dr. Taskin received the ACM SIGDA Distinguished Service Award in 2012.<br /> <br /> <br /> * Ying Teng received the George Hill, Jr. fellowship from Drexel University in 2012.<br /> <br /> <br /> * See our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> <br /> * Ying Teng received the N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2011.<br /> <br /> <br /> * Here is the report for the Drexel Office of International Programs travel award for Dr. Taskin to ISCAS'11. [http://www.drexel.edu/international/assets/pdf/ita/faculty/2011-Taskin_Baris.pdf]<br /> &lt;gallery&gt;<br /> File:Facultyspotlight.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ying Teng's first journal paper &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot; is featured on the cover of the Journal of Low Power Electronics (JOLPE) in December 2010. Check out the [[Publications]] page for details.<br /> &lt;gallery&gt;<br /> File:JOLPEDec10.jpg<br /> File:jlp64Fig.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ankit More received the George Hill, Jr. fellowship from Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Ying Teng presented their work in University Booth, at the ACM/IEEE Design Automation Conference in Anaheim, CA, in 2010.<br /> &lt;gallery&gt;<br /> File:Jianchao_2010_dac.JPG<br /> File:Ying_2010_dac.JPG<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Sharat Chandra recipient of the Young Student Support Program Award for the Design Automation Conference in Anaheim, CA in 2010:<br /> [http://www.sigda.org/youngstudent.html Young Student Support Program DAC]<br /> <br /> <br /> * The NSF-funded REU Site opportunity on &quot;Computing for Power and Energy&quot; directed by Dr. Taskin is starting in Summer 2010: [http://reu.ece.drexel.edu REU Site on Computing for Power and Energy: The Old, The New and The Renewable]. This site will run for the next three years.<br /> &lt;gallery&gt;<br /> File:DrexelREU2010web.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Vinayak received the first N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote presented their work in University Booth and Ph.D. Forum, respectively, at the ACM/IEEE Design Automation Conference in San Francisco, CA, in 2009.<br /> &lt;gallery&gt;<br /> File:dac2009_jianchao.jpg<br /> File:dac2009_vinayak.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote participated in the SIGDA CADAthlon at ICCAD 2008 in San Jose, CA.<br /> &lt;gallery&gt;<br /> File:cadathlon080.jpg<br /> File:cadathlon081.jpg<br /> File:cadathlon082.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Accepting the ''A. Richard Newton Award'' at the ACM/IEEE Design Automation Conference in 2007.<br /> &lt;gallery&gt;<br /> File:dac2007.jpg<br /> File:dac20071.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Drexel Senior Design team, also winners of the CE award, presented at the University Booth at the ACM/IEEE Design Automation Conference in San Diego, CA, in 2007.<br /> &lt;gallery&gt;<br /> File:senior07.jpg<br /> File:senior071.jpg<br /> File:senior072.jpg<br /> &lt;/gallery&gt;</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=News/Events&diff=7714 2025-02-05T15:21:48Z

<p>Taskin: </p> <hr /> <div><br /> * Scott is now Dr. Scott Lerner, Summer 2024.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2023-2024.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Fall 2023-2024.<br /> <br /> * Yilmaz Gonul participated in DAC Young Fellows program at DAC 2023. <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2022-2023.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Winter 2022-2023.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2021-2022.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Winter 2020.<br /> <br /> * Dr. Taskin is delivering the keynote &quot;On-Chip Wireless Interconnect Paradigm&quot; at [http://www.nocarc.org 12th International Workshop on Network on Chip Architectures (NoCARC) 2019], held in conjuction with MICRO 2019 in Columbus Ohio.<br /> &lt;gallery&gt;<br /> File:NoCARC19Keynote.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Mike Lui is interning at Facebook Fall 2019.<br /> <br /> <br /> * Scott Lerner is interning at Intel Summer/Fall 2019. <br /> <br /> <br /> * Vasil is now Dr. Vasil Pano, Summer 2019.<br /> <br /> <br /> * Leo is now Dr. Leo Filippini, Spring 2019.<br /> <br /> <br /> * Our resonant clock team RotaSyn participated in National Science Foundation I-Corps Short Course at Drexel University organized by Upstate NY I-Corps Node, March 2019.<br /> &lt;gallery&gt;<br /> File:Rotasyn-Session5Cover.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is On for Winter 2019.<br /> <br /> <br /> * Scott Lerner received the Koerner Family Award in 2019.<br /> <br /> <br /> * Dr. Taskin is the General Chair for ACM GLSVLSI 2019 in Tysons Corner, VA.<br /> &lt;gallery&gt;<br /> File:GLSVLSI19Chair.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> * Dr. Taskin elected the chair of [http://ieee-cas.org/community/technical-committees/vlsi-systems-applications-technical-committee-vsatc IEEE Circuits and Systems Society's (CASS) Technical Committee on VLSI Systems and Applications (CAS VSA-TC)], 2018-2020.<br /> &lt;gallery&gt;<br /> File:VSATCChair.png<br /> &lt;/gallery&gt;<br /> <br /> * Vasil Pano received the Nihat Bilgutay Award in 2018.<br /> <br /> <br /> * Mike Lui received the Koerner Family Award in 2018. <br /> <br /> <br /> * Karthik Sangaiah, Scott Lerner, and Ragh Kuttappa receive the Weggel Family Fellowship in 2018.<br /> <br /> <br /> * Scott Lerner, Vasil Pano and Baris Taskin won the first place at the 10th Annual Drexel IEEE Graduate Symposium poster competition for their work on &quot;NoC Router Lifetime Improvement Using Per-Port Router Utilization&quot;, accepted at IEEE International Symposium on Circuits and Systems (ISCAS).<br /> <br /> <br /> * Completed CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2018.<br /> <br /> <br /> * Dr. Taskin is the TPC co-chair for ACM GLSVLSI 2018 in Chicago, IL.<br /> <br /> <br /> * Granted United States Patent No. 9,773,079, ``Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits'', Inventors: Taskin and Sitik, 2017<br /> <br /> <br /> *Granted United States Patent No. 9,484,896, ``Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling'', Inventors: Taskin and Teng, 2017<br /> <br /> <br /> * Scott Lerner, Vasil Pano, and Leo Filippini receive ECE awards in 2017.<br /> <br /> <br /> * Mike Lui and Kartik Sangaiah will give a tutorial on &quot;Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation&quot; @ International Symposium on Workload Characterization (IISWC), 2016.<br /> <br /> <br /> * Can Sitik received Honorable mention for the Outstanding Dissertation Award at Drexel College of Engineering graduation in 2016.<br /> <br /> <br /> * Scott received the Frank &amp; Agnes Seaman fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2016.<br /> <br /> <br /> * Leo received the Carleone fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2016.<br /> <br /> <br /> * Vasil Pano and Scott Lerner recipients of the A. Richard Newton Young Student Fellow Program award for the Design Automation Conference in Austin, TX in 2016.<br /> <br /> <br /> * Junghoon Oh, a PhD student from JAIST, Japan, joins the lab as a visiting researcher for 2016.<br /> <br /> <br /> * IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Spring 2016.<br /> &lt;gallery&gt;<br /> File:2016_Sp_symposiaFlyer.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * The first IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium talk for Spring 2016.<br /> &lt;gallery&gt;<br /> File:2016_Sp_symposium_01.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2016.<br /> &lt;gallery&gt;<br /> File:symposia-winterFlyer16.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Prof. Taskin is the General Chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016 [http://sliponline.org]<br /> <br /> <br /> * Dr. Taskin received the Outstanding Research award from the Drexel ECE Department in 2015.<br /> <br /> <br /> * Dr. Taskin started and will serve as the treasurer of the IEEE Central Pennsylvania, Pittsburgh, Philadelphia Joint Sections Council of Electronic Design Automation (CEDA) Chapter.<br /> <br /> <br /> * Tutorial delivered at ICCD 2015: &quot;Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation&quot; @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University, Stephan Diestelhorst, ARM Research).<br /> <br /> <br /> * Drexel Computer Engineering Graduate Symposium program for Fall, Winter and Spring 2015.<br /> &lt;gallery&gt;<br /> File:symposia-fallFlyer15.png<br /> File:symposia-winterFlyer15.png<br /> File:symposia-springFlyer15.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Two familiar faces on the cover of the 2014-15 report from the Drexel Fellowship Office; Paco as a mentor (GRFP 2014) and Scott for having received the NDSEG and GRFP this year in 2015. [http://www.drexel.edu/fellowships/about/overview/Annual%20Report/ Drexel Fellowship Office 2014-2015 Report]<br /> <br /> <br /> * Mike Lui will give a tutorial on &quot;Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace&quot; @ International Symposium on Workload Characterization (IISWC), 2015.<br /> &lt;gallery&gt;<br /> File:IISWC_flyer.png<br /> &lt;/gallery&gt;<br /> <br /> * Dr. Taskin and [http://nanocas.ece.stonybrook.edu/salman/ Dr. Salman (Stony Brook University)] gave a tutorial on &quot;Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances&quot; @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015 in Lisbon, Portugal [http://www.iscas2015.org/program/tutorials/].<br /> <br /> <br /> * Renamed &quot;Drexel VLSI Lab&quot; to &quot;Drexel VLSI and Architecture Lab&quot; to more accurately reflect the current [[Research]] portfolio.<br /> <br /> <br /> * Scott Lerner received 52nd DAC Richard Newton Young Fellowship from Design Automation Conference in 2015.<br /> <br /> <br /> * Scott Lerner received the DoD NSDEG fellowship (declined) in 2015.<br /> <br /> <br /> * Scott Lerner received the NSF GRFP Fellowship in 2015. [http://drexel.edu/fellowships/studentprofiles/profiles/Scott%20Lerner/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:ScottNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Giordano Salvador (REU 2013, REU 2014, also independent research, UPenn) received the NSF GRFP Fellowship in 2015, will attend UIUC.<br /> <br /> <br /> * Michael Miller (REU 2013, Goshen College) received the NSF GRFP Fellowship in 2015, will attend CMU.<br /> <br /> <br /> * Can Sitik and Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2015.<br /> <br /> <br /> * Prof. Taskin is the TPC chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2015 [http://sliponline.org]<br /> <br /> <br /> * Scott Lerner received the A. Richard Newton Young Student Fellow Program travel grant from Design Automation Conference in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the NSF GRFP Fellowship in 2014. [http://drexel.edu/fellowships/studentprofiles/profiles/Karthik%20Sangaiah/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:PacoNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Can Sitik received the Leroy L. Rosser fellowship from Drexel University in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2014.<br /> <br /> <br /> * Best paper nomination for Can Sitik at the ACM GLSVLSI 2013 for the paper entitled [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]].<br /> <br /> <br /> * Can Sitik received the George Hill, Jr. fellowship from Drexel University in 2013.<br /> <br /> <br /> * Prof. Taskin is selected the &quot;Young Electrical Engineer of the Year 2013&quot; by the IEEE Philadelphia Section.<br /> <br /> <br /> * Prof. Taskin organized and presented a tutorial on &quot;Resonant Clocking&quot; with Prof. Matthew Guthaus of UCSC and Drexel VLSI Lab Alumni Dr. Vinayak Honkote of Intel at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012 in San Jose, CA. [http://iccad.com/2012_event_details?id=149-10-D program link]<br /> <br /> <br /> * Drexel student newspaper article on hybrid wireless NoC project [http://thetriangle.org/2012/08/31/antennas-allow-microchips-to-go-wireless/ Drexel Triangle link]<br /> * News release from Drexel about our hybrid wireless NoC project [http://www.drexel.edu/now/news-media/releases/archive/2012/August/Wireless-Network-on-Chip/ August 2012 DrexelNOW link] <br /> &lt;gallery&gt;<br /> File:Chip_CourtesyBarisTaskin-300x225.jpg<br /> File:microchip.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Dr. Taskin received the ACM SIGDA Distinguished Service Award in 2012.<br /> <br /> <br /> * Ying Teng received the George Hill, Jr. fellowship from Drexel University in 2012.<br /> <br /> <br /> * See our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> <br /> * Ying Teng received the N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2011.<br /> <br /> <br /> * Here is the report for the Drexel Office of International Programs travel award for Dr. Taskin to ISCAS'11. [http://www.drexel.edu/international/assets/pdf/ita/faculty/2011-Taskin_Baris.pdf]<br /> &lt;gallery&gt;<br /> File:Facultyspotlight.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ying Teng's first journal paper &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot; is featured on the cover of the Journal of Low Power Electronics (JOLPE) in December 2010. Check out the [[Publications]] page for details.<br /> &lt;gallery&gt;<br /> File:JOLPEDec10.jpg<br /> File:jlp64Fig.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ankit More received the George Hill, Jr. fellowship from Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Ying Teng presented their work in University Booth, at the ACM/IEEE Design Automation Conference in Anaheim, CA, in 2010.<br /> &lt;gallery&gt;<br /> File:Jianchao_2010_dac.JPG<br /> File:Ying_2010_dac.JPG<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Sharat Chandra recipient of the Young Student Support Program Award for the Design Automation Conference in Anaheim, CA in 2010:<br /> [http://www.sigda.org/youngstudent.html Young Student Support Program DAC]<br /> <br /> <br /> * The NSF-funded REU Site opportunity on &quot;Computing for Power and Energy&quot; directed by Dr. Taskin is starting in Summer 2010: [http://reu.ece.drexel.edu REU Site on Computing for Power and Energy: The Old, The New and The Renewable]. This site will run for the next three years.<br /> &lt;gallery&gt;<br /> File:DrexelREU2010web.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Vinayak received the first N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote presented their work in University Booth and Ph.D. Forum, respectively, at the ACM/IEEE Design Automation Conference in San Francisco, CA, in 2009.<br /> &lt;gallery&gt;<br /> File:dac2009_jianchao.jpg<br /> File:dac2009_vinayak.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote participated in the SIGDA CADAthlon at ICCAD 2008 in San Jose, CA.<br /> &lt;gallery&gt;<br /> File:cadathlon080.jpg<br /> File:cadathlon081.jpg<br /> File:cadathlon082.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Accepting the ''A. Richard Newton Award'' at the ACM/IEEE Design Automation Conference in 2007.<br /> &lt;gallery&gt;<br /> File:dac2007.jpg<br /> File:dac20071.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Drexel Senior Design team, also winners of the CE award, presented at the University Booth at the ACM/IEEE Design Automation Conference in San Diego, CA, in 2007.<br /> &lt;gallery&gt;<br /> File:senior07.jpg<br /> File:senior071.jpg<br /> File:senior072.jpg<br /> &lt;/gallery&gt;</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=News/Events&diff=7713 2025-02-05T15:19:20Z

<p>Taskin: </p> <hr /> <div><br /> * Scott is now Dr. Scott Lerner, Summer 2024.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Fall 2023-2024.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2023-2024.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Winter 2022-2023.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Spring 2021-2022.<br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is on for Winter 2020.<br /> <br /> * Dr. Taskin is delivering the keynote &quot;On-Chip Wireless Interconnect Paradigm&quot; at [http://www.nocarc.org 12th International Workshop on Network on Chip Architectures (NoCARC) 2019], held in conjuction with MICRO 2019 in Columbus Ohio.<br /> &lt;gallery&gt;<br /> File:NoCARC19Keynote.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Mike Lui is interning at Facebook Fall 2019.<br /> <br /> <br /> * Scott Lerner is interning at Intel Summer/Fall 2019. <br /> <br /> <br /> * Vasil is now Dr. Vasil Pano, Summer 2019.<br /> <br /> <br /> * Leo is now Dr. Leo Filippini, Spring 2019.<br /> <br /> <br /> * Our resonant clock team RotaSyn participated in National Science Foundation I-Corps Short Course at Drexel University organized by Upstate NY I-Corps Node, March 2019.<br /> &lt;gallery&gt;<br /> File:Rotasyn-Session5Cover.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * CEDA sponsored Drexel Computer Engineering Graduate Symposium program is On for Winter 2019.<br /> <br /> <br /> * Scott Lerner received the Koerner Family Award in 2019.<br /> <br /> <br /> * Dr. Taskin is the General Chair for ACM GLSVLSI 2019 in Tysons Corner, VA.<br /> &lt;gallery&gt;<br /> File:GLSVLSI19Chair.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> * Dr. Taskin elected the chair of [http://ieee-cas.org/community/technical-committees/vlsi-systems-applications-technical-committee-vsatc IEEE Circuits and Systems Society's (CASS) Technical Committee on VLSI Systems and Applications (CAS VSA-TC)], 2018-2020.<br /> &lt;gallery&gt;<br /> File:VSATCChair.png<br /> &lt;/gallery&gt;<br /> <br /> * Vasil Pano received the Nihat Bilgutay Award in 2018.<br /> <br /> <br /> * Mike Lui received the Koerner Family Award in 2018. <br /> <br /> <br /> * Karthik Sangaiah, Scott Lerner, and Ragh Kuttappa receive the Weggel Family Fellowship in 2018.<br /> <br /> <br /> * Scott Lerner, Vasil Pano and Baris Taskin won the first place at the 10th Annual Drexel IEEE Graduate Symposium poster competition for their work on &quot;NoC Router Lifetime Improvement Using Per-Port Router Utilization&quot;, accepted at IEEE International Symposium on Circuits and Systems (ISCAS).<br /> <br /> <br /> * Completed CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2018.<br /> <br /> <br /> * Dr. Taskin is the TPC co-chair for ACM GLSVLSI 2018 in Chicago, IL.<br /> <br /> <br /> * Granted United States Patent No. 9,773,079, ``Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits'', Inventors: Taskin and Sitik, 2017<br /> <br /> <br /> *Granted United States Patent No. 9,484,896, ``Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling'', Inventors: Taskin and Teng, 2017<br /> <br /> <br /> * Scott Lerner, Vasil Pano, and Leo Filippini receive ECE awards in 2017.<br /> <br /> <br /> * Mike Lui and Kartik Sangaiah will give a tutorial on &quot;Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation&quot; @ International Symposium on Workload Characterization (IISWC), 2016.<br /> <br /> <br /> * Can Sitik received Honorable mention for the Outstanding Dissertation Award at Drexel College of Engineering graduation in 2016.<br /> <br /> <br /> * Scott received the Frank &amp; Agnes Seaman fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2016.<br /> <br /> <br /> * Leo received the Carleone fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2016.<br /> <br /> <br /> * Vasil Pano and Scott Lerner recipients of the A. Richard Newton Young Student Fellow Program award for the Design Automation Conference in Austin, TX in 2016.<br /> <br /> <br /> * Junghoon Oh, a PhD student from JAIST, Japan, joins the lab as a visiting researcher for 2016.<br /> <br /> <br /> * IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Spring 2016.<br /> &lt;gallery&gt;<br /> File:2016_Sp_symposiaFlyer.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * The first IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium talk for Spring 2016.<br /> &lt;gallery&gt;<br /> File:2016_Sp_symposium_01.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2016.<br /> &lt;gallery&gt;<br /> File:symposia-winterFlyer16.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Prof. Taskin is the General Chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016 [http://sliponline.org]<br /> <br /> <br /> * Dr. Taskin received the Outstanding Research award from the Drexel ECE Department in 2015.<br /> <br /> <br /> * Dr. Taskin started and will serve as the treasurer of the IEEE Central Pennsylvania, Pittsburgh, Philadelphia Joint Sections Council of Electronic Design Automation (CEDA) Chapter.<br /> <br /> <br /> * Tutorial delivered at ICCD 2015: &quot;Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation&quot; @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University, Stephan Diestelhorst, ARM Research).<br /> <br /> <br /> * Drexel Computer Engineering Graduate Symposium program for Fall, Winter and Spring 2015.<br /> &lt;gallery&gt;<br /> File:symposia-fallFlyer15.png<br /> File:symposia-winterFlyer15.png<br /> File:symposia-springFlyer15.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Two familiar faces on the cover of the 2014-15 report from the Drexel Fellowship Office; Paco as a mentor (GRFP 2014) and Scott for having received the NDSEG and GRFP this year in 2015. [http://www.drexel.edu/fellowships/about/overview/Annual%20Report/ Drexel Fellowship Office 2014-2015 Report]<br /> <br /> <br /> * Mike Lui will give a tutorial on &quot;Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace&quot; @ International Symposium on Workload Characterization (IISWC), 2015.<br /> &lt;gallery&gt;<br /> File:IISWC_flyer.png<br /> &lt;/gallery&gt;<br /> <br /> * Dr. Taskin and [http://nanocas.ece.stonybrook.edu/salman/ Dr. Salman (Stony Brook University)] gave a tutorial on &quot;Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances&quot; @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015 in Lisbon, Portugal [http://www.iscas2015.org/program/tutorials/].<br /> <br /> <br /> * Renamed &quot;Drexel VLSI Lab&quot; to &quot;Drexel VLSI and Architecture Lab&quot; to more accurately reflect the current [[Research]] portfolio.<br /> <br /> <br /> * Scott Lerner received 52nd DAC Richard Newton Young Fellowship from Design Automation Conference in 2015.<br /> <br /> <br /> * Scott Lerner received the DoD NSDEG fellowship (declined) in 2015.<br /> <br /> <br /> * Scott Lerner received the NSF GRFP Fellowship in 2015. [http://drexel.edu/fellowships/studentprofiles/profiles/Scott%20Lerner/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:ScottNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Giordano Salvador (REU 2013, REU 2014, also independent research, UPenn) received the NSF GRFP Fellowship in 2015, will attend UIUC.<br /> <br /> <br /> * Michael Miller (REU 2013, Goshen College) received the NSF GRFP Fellowship in 2015, will attend CMU.<br /> <br /> <br /> * Can Sitik and Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2015.<br /> <br /> <br /> * Prof. Taskin is the TPC chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2015 [http://sliponline.org]<br /> <br /> <br /> * Scott Lerner received the A. Richard Newton Young Student Fellow Program travel grant from Design Automation Conference in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the NSF GRFP Fellowship in 2014. [http://drexel.edu/fellowships/studentprofiles/profiles/Karthik%20Sangaiah/ Drexel Fellowship Office news]<br /> &lt;gallery&gt;<br /> File:PacoNSF.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Can Sitik received the Leroy L. Rosser fellowship from Drexel University in 2014.<br /> <br /> <br /> * Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2014.<br /> <br /> <br /> * Best paper nomination for Can Sitik at the ACM GLSVLSI 2013 for the paper entitled [[media:Can_GLSVLSI13.pdf‎|&quot;Skew-Bounded Low Swing Clock Tree Optimization&quot;]].<br /> <br /> <br /> * Can Sitik received the George Hill, Jr. fellowship from Drexel University in 2013.<br /> <br /> <br /> * Prof. Taskin is selected the &quot;Young Electrical Engineer of the Year 2013&quot; by the IEEE Philadelphia Section.<br /> <br /> <br /> * Prof. Taskin organized and presented a tutorial on &quot;Resonant Clocking&quot; with Prof. Matthew Guthaus of UCSC and Drexel VLSI Lab Alumni Dr. Vinayak Honkote of Intel at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012 in San Jose, CA. [http://iccad.com/2012_event_details?id=149-10-D program link]<br /> <br /> <br /> * Drexel student newspaper article on hybrid wireless NoC project [http://thetriangle.org/2012/08/31/antennas-allow-microchips-to-go-wireless/ Drexel Triangle link]<br /> * News release from Drexel about our hybrid wireless NoC project [http://www.drexel.edu/now/news-media/releases/archive/2012/August/Wireless-Network-on-Chip/ August 2012 DrexelNOW link] <br /> &lt;gallery&gt;<br /> File:Chip_CourtesyBarisTaskin-300x225.jpg<br /> File:microchip.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Dr. Taskin received the ACM SIGDA Distinguished Service Award in 2012.<br /> <br /> <br /> * Ying Teng received the George Hill, Jr. fellowship from Drexel University in 2012.<br /> <br /> <br /> * See our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> <br /> * Ying Teng received the N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2011.<br /> <br /> <br /> * Here is the report for the Drexel Office of International Programs travel award for Dr. Taskin to ISCAS'11. [http://www.drexel.edu/international/assets/pdf/ita/faculty/2011-Taskin_Baris.pdf]<br /> &lt;gallery&gt;<br /> File:Facultyspotlight.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ying Teng's first journal paper &quot;Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect&quot; is featured on the cover of the Journal of Low Power Electronics (JOLPE) in December 2010. Check out the [[Publications]] page for details.<br /> &lt;gallery&gt;<br /> File:JOLPEDec10.jpg<br /> File:jlp64Fig.png<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Ankit More received the George Hill, Jr. fellowship from Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Ying Teng presented their work in University Booth, at the ACM/IEEE Design Automation Conference in Anaheim, CA, in 2010.<br /> &lt;gallery&gt;<br /> File:Jianchao_2010_dac.JPG<br /> File:Ying_2010_dac.JPG<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Sharat Chandra recipient of the Young Student Support Program Award for the Design Automation Conference in Anaheim, CA in 2010:<br /> [http://www.sigda.org/youngstudent.html Young Student Support Program DAC]<br /> <br /> <br /> * The NSF-funded REU Site opportunity on &quot;Computing for Power and Energy&quot; directed by Dr. Taskin is starting in Summer 2010: [http://reu.ece.drexel.edu REU Site on Computing for Power and Energy: The Old, The New and The Renewable]. This site will run for the next three years.<br /> &lt;gallery&gt;<br /> File:DrexelREU2010web.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Vinayak received the first N. Bilgutay fellowship from the Department of Electrical &amp; Computer Engineering, Drexel University in 2010.<br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote presented their work in University Booth and Ph.D. Forum, respectively, at the ACM/IEEE Design Automation Conference in San Francisco, CA, in 2009.<br /> &lt;gallery&gt;<br /> File:dac2009_jianchao.jpg<br /> File:dac2009_vinayak.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> <br /> * Jianchao Lu and Vinayak Honkote participated in the SIGDA CADAthlon at ICCAD 2008 in San Jose, CA.<br /> &lt;gallery&gt;<br /> File:cadathlon080.jpg<br /> File:cadathlon081.jpg<br /> File:cadathlon082.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Accepting the ''A. Richard Newton Award'' at the ACM/IEEE Design Automation Conference in 2007.<br /> &lt;gallery&gt;<br /> File:dac2007.jpg<br /> File:dac20071.jpg<br /> &lt;/gallery&gt;<br /> <br /> <br /> * Drexel Senior Design team, also winners of the CE award, presented at the University Booth at the ACM/IEEE Design Automation Conference in San Diego, CA, in 2007.<br /> &lt;gallery&gt;<br /> File:senior07.jpg<br /> File:senior071.jpg<br /> File:senior072.jpg<br /> &lt;/gallery&gt;</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=7712 2025-02-05T15:15:33Z

<p>Taskin: </p> <hr /> <div>Drexel VANDAL consists of a research group of computer engineers and electrical engineers tackling big engineering problems of building sophisticated systems. <br /> <br /> Some project descriptions are as follows.<br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated), [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, Ceyhun Kayan, Sief Atari (quit), [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (1232164, [[2008629]]), Mosis<br /> <br /> Collaborator(s): Kapil Dandekar (Wireless Communication Systems, Co-PI)<br /> <br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, [[Leo Filippini]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Emre Salman SUNY-Stony Brook, Diane Lim (Penn School of Medicine), Lunal Khuon (RF, analog, and biomedical ICs).<br /> <br /> <br /> == Unconventional Computing using Oscillators ==<br /> <br /> Unconventional Computing using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> <br /> Ph.D. Student(s): [[Nicholas Sica]], [[Yilmaz Gonul]]<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Ragh Kuttappa (Intel), Vinayak Honkote (Intel)<br /> <br /> <br /> == Perturbation Biology Modeling==<br /> <br /> The project develops machine learning approaches to evaluate and predict mechanisms of adaptation to external perturbations in biological systems. While providing a new and fundamental understanding of biological systems, we develop and apply the ML tools in the context of a model paradigm, emergence of resistance to targeted drugs. Machine learning toolset is ideal in identifying relationships that are non trivial, leading to deep understanding of dependencies that exist in combinations and in time. With the help of machine learning and data, &quot;target scores&quot; of the potential treatment responses can be determined in increased precision. Simulation of potential treatments can allow researchers to develop novel biological insights related to the adaptive working mechanism of cancer. As a next step, the developed tool can be incorporated with drug discovery related studies. Observing the short and long-term effects of new drug combinations would accelerate the drug discovery procedure. The developed target score prediction model can be used to monitor the effects of proposed drug combinations as well. <br /> <br /> Ph.D. Student(s): Ceyhun Kayan<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Anil Korkut (MD Anderson)<br /> <br /> <br /> = Previous Projects = <br /> <br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Leo Filippini]] (graduated), [[Can Sitik]] (graduated)<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Collaborator(s): Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Can Sitik]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> <br /> == CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> <br /> Check our Software Release: [[SynchroTrace]]<br /> <br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]] (graduated), [[Michael Lui]], [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Mark Hempstead, Tufts (Computer Architecture)<br /> <br /> <br /> == Energy Efficient Computing with OptoElectronics==<br /> <br /> In order to achieve energy efficient computing for systems ranging from datacenters down to mobile electronics, novel devices, techniques, and methodologies are necessary to reduce the terawatts of power consumed by computational devices. We are proposing an effort to bring together researchers from all levels of the device to systems hierarchy (Devices -&gt; Circuits -&gt; Architecture -&gt; Systems -&gt; Data Center) in a vertically integrated approach addressing the (energy) challenges of future computing devices. Our vision is to build upon novel optoelectronic devices capable of computing a bit while consuming attojoules (10E-18 J) of energy, and progress to energy efficient techniques and methodologies for data centers that consume terawatts of power from the electrical grid. Energy efficient innovations at the circuits, systems/interconnect, architecture, and server/mobile/datacenter platform level have the potential to significantly reduce overall power consumption and address this grand challenge in energy needs. Our team is to leverage the energy efficiency of novel optoelectronic elements, and focus research efforts on reducing the total power consumption of electronic devices through energy efficient techniques and methodologies for IC chips, devices, and ultimately data centers that consume terawatts of power from the electrical grid. <br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Bahram Nabet (Photonics), Ioannis Savidis (Circuits and Systems), Naga Kandasamy (HPC), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).<br /> <br /> <br /> == GPU System Co-design ==<br /> <br /> Similar to CMP-NoC Design challenges, the co-design of hardware and software on GPU systems is explored. Platform independent dependencies of threads are analyzed on GPUs, leading to the analysis of software and hardware co-design principles.<br /> <br /> Ph.D. Student(s): [[Michael Lui]], [[Karthik Sangaiah]] (graduated)<br /> <br /> Sponsor(s): Samsung GRO <br /> <br /> Collaborator(s): Mark Hempstead (Computer Architecture)<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=7711 2025-02-05T15:15:03Z

<p>Taskin: </p> <hr /> <div>Drexel VANDAL consists of a research group of computer engineers and electrical engineers tackling big engineering problems of building sophisticated systems. Some of the projects are in:<br /> * Exa-scale computing systems<br /> * Smart energy/Smart home systems<br /> * IoT processor design<br /> * Bio-Implantable systems<br /> * 5G communication systems<br /> * Algorithms and software for IoT hardware and software design, including machine learning<br /> * Unconventional computing using oscillators<br /> * Perturbation Biology Modeling<br /> <br /> <br /> Some project descriptions are as follows.<br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated), [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, Ceyhun Kayan, Sief Atari (quit), [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (1232164, [[2008629]]), Mosis<br /> <br /> Collaborator(s): Kapil Dandekar (Wireless Communication Systems, Co-PI)<br /> <br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, [[Leo Filippini]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Emre Salman SUNY-Stony Brook, Diane Lim (Penn School of Medicine), Lunal Khuon (RF, analog, and biomedical ICs).<br /> <br /> <br /> == Unconventional Computing using Oscillators ==<br /> <br /> Unconventional Computing using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> <br /> Ph.D. Student(s): [[Nicholas Sica]], [[Yilmaz Gonul]]<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Ragh Kuttappa (Intel), Vinayak Honkote (Intel)<br /> <br /> <br /> == Perturbation Biology Modeling==<br /> <br /> The project develops machine learning approaches to evaluate and predict mechanisms of adaptation to external perturbations in biological systems. While providing a new and fundamental understanding of biological systems, we develop and apply the ML tools in the context of a model paradigm, emergence of resistance to targeted drugs. Machine learning toolset is ideal in identifying relationships that are non trivial, leading to deep understanding of dependencies that exist in combinations and in time. With the help of machine learning and data, &quot;target scores&quot; of the potential treatment responses can be determined in increased precision. Simulation of potential treatments can allow researchers to develop novel biological insights related to the adaptive working mechanism of cancer. As a next step, the developed tool can be incorporated with drug discovery related studies. Observing the short and long-term effects of new drug combinations would accelerate the drug discovery procedure. The developed target score prediction model can be used to monitor the effects of proposed drug combinations as well. <br /> <br /> Ph.D. Student(s): Ceyhun Kayan<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Anil Korkut (MD Anderson)<br /> <br /> <br /> = Previous Projects = <br /> <br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Leo Filippini]] (graduated), [[Can Sitik]] (graduated)<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Collaborator(s): Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Can Sitik]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> <br /> == CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> <br /> Check our Software Release: [[SynchroTrace]]<br /> <br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]] (graduated), [[Michael Lui]], [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Mark Hempstead, Tufts (Computer Architecture)<br /> <br /> <br /> == Energy Efficient Computing with OptoElectronics==<br /> <br /> In order to achieve energy efficient computing for systems ranging from datacenters down to mobile electronics, novel devices, techniques, and methodologies are necessary to reduce the terawatts of power consumed by computational devices. We are proposing an effort to bring together researchers from all levels of the device to systems hierarchy (Devices -&gt; Circuits -&gt; Architecture -&gt; Systems -&gt; Data Center) in a vertically integrated approach addressing the (energy) challenges of future computing devices. Our vision is to build upon novel optoelectronic devices capable of computing a bit while consuming attojoules (10E-18 J) of energy, and progress to energy efficient techniques and methodologies for data centers that consume terawatts of power from the electrical grid. Energy efficient innovations at the circuits, systems/interconnect, architecture, and server/mobile/datacenter platform level have the potential to significantly reduce overall power consumption and address this grand challenge in energy needs. Our team is to leverage the energy efficiency of novel optoelectronic elements, and focus research efforts on reducing the total power consumption of electronic devices through energy efficient techniques and methodologies for IC chips, devices, and ultimately data centers that consume terawatts of power from the electrical grid. <br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Bahram Nabet (Photonics), Ioannis Savidis (Circuits and Systems), Naga Kandasamy (HPC), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).<br /> <br /> <br /> == GPU System Co-design ==<br /> <br /> Similar to CMP-NoC Design challenges, the co-design of hardware and software on GPU systems is explored. Platform independent dependencies of threads are analyzed on GPUs, leading to the analysis of software and hardware co-design principles.<br /> <br /> Ph.D. Student(s): [[Michael Lui]], [[Karthik Sangaiah]] (graduated)<br /> <br /> Sponsor(s): Samsung GRO <br /> <br /> Collaborator(s): Mark Hempstead (Computer Architecture)<br /> <br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=7710 2025-02-05T15:13:50Z

<p>Taskin: </p> <hr /> <div>Drexel VANDAL consists of a research group of computer engineers and electrical engineers tackling big engineering problems of building sophisticated systems. Some of the projects are in:<br /> * Exa-scale computing systems<br /> * Smart energy/Smart home systems<br /> * IoT processor design<br /> * Bio-Implantable systems<br /> * 5G communication systems<br /> * Algorithms and software for IoT hardware and software design, including machine learning<br /> * Unconventional computing using oscillators<br /> * Perturbation Biology Modeling<br /> <br /> <br /> Some project descriptions are as follows.<br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated), [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, Ceyhun Kayan, Sief Atari (quit), [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (1232164, [[2008629]]), Mosis<br /> <br /> Collaborator(s): Kapil Dandekar (Wireless Communication Systems, Co-PI)<br /> <br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, [[Leo Filippini]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Emre Salman SUNY-Stony Brook, Diane Lim (Penn School of Medicine), Lunal Khuon (RF, analog, and biomedical ICs).<br /> <br /> <br /> == Unconventional Computing using Oscillators ==<br /> <br /> Unconventional Computing using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> <br /> Ph.D. Student(s): [[Nicholas Sica]], [[Yilmaz Gonul]]<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Ragh Kuttappa (Intel), Vinayak Honkote (Intel)<br /> <br /> == Perturbation Biology Modeling==<br /> <br /> The project develops machine learning approaches to evaluate and predict mechanisms of adaptation to external perturbations in biological systems. While providing a new and fundamental understanding of biological systems, we develop and apply the ML tools in the context of a model paradigm, emergence of resistance to targeted drugs. Machine learning toolset is ideal in identifying relationships that are non trivial, leading to deep understanding of dependencies that exist in combinations and in time. With the help of machine learning and data, &quot;target scores&quot; of the potential treatment responses can be determined in increased precision. Simulation of potential treatments can allow researchers to develop novel biological insights related to the adaptive working mechanism of cancer. As a next step, the developed tool can be incorporated with drug discovery related studies. Observing the short and long-term effects of new drug combinations would accelerate the drug discovery procedure. The developed target score prediction model can be used to monitor the effects of proposed drug combinations as well. <br /> <br /> Ph.D. Student(s): Ceyhun Kayan<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Anil Korkut (MD Anderson)<br /> <br /> <br /> = Previous Projects = <br /> <br /> <br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Leo Filippini]] (graduated), [[Can Sitik]] (graduated)<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Collaborator(s): Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Can Sitik]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> <br /> == CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> <br /> Check our Software Release: [[SynchroTrace]]<br /> <br /> <br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]] (graduated), [[Michael Lui]], [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Mark Hempstead, Tufts (Computer Architecture)<br /> <br /> <br /> == Energy Efficient Computing with OptoElectronics==<br /> <br /> In order to achieve energy efficient computing for systems ranging from datacenters down to mobile electronics, novel devices, techniques, and methodologies are necessary to reduce the terawatts of power consumed by computational devices. We are proposing an effort to bring together researchers from all levels of the device to systems hierarchy (Devices -&gt; Circuits -&gt; Architecture -&gt; Systems -&gt; Data Center) in a vertically integrated approach addressing the (energy) challenges of future computing devices. Our vision is to build upon novel optoelectronic devices capable of computing a bit while consuming attojoules (10E-18 J) of energy, and progress to energy efficient techniques and methodologies for data centers that consume terawatts of power from the electrical grid. Energy efficient innovations at the circuits, systems/interconnect, architecture, and server/mobile/datacenter platform level have the potential to significantly reduce overall power consumption and address this grand challenge in energy needs. Our team is to leverage the energy efficiency of novel optoelectronic elements, and focus research efforts on reducing the total power consumption of electronic devices through energy efficient techniques and methodologies for IC chips, devices, and ultimately data centers that consume terawatts of power from the electrical grid. <br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Bahram Nabet (Photonics), Ioannis Savidis (Circuits and Systems), Naga Kandasamy (HPC), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).<br /> <br /> <br /> <br /> == GPU System Co-design ==<br /> <br /> Similar to CMP-NoC Design challenges, the co-design of hardware and software on GPU systems is explored. Platform independent dependencies of threads are analyzed on GPUs, leading to the analysis of software and hardware co-design principles.<br /> <br /> Ph.D. Student(s): [[Michael Lui]], [[Karthik Sangaiah]] (graduated)<br /> <br /> Sponsor(s): Samsung GRO <br /> <br /> Collaborator(s): Mark Hempstead (Computer Architecture)<br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=7709 2025-02-05T15:09:46Z

<p>Taskin: </p> <hr /> <div>Drexel VANDAL consists of a research group of computer engineers and electrical engineers tackling big engineering problems of building sophisticated systems. Some of the projects are in:<br /> * Exa-scale computing systems<br /> * Smart energy/Smart home systems<br /> * IoT processor design<br /> * Bio-Implantable systems<br /> * 5G communication systems<br /> * Algorithms and software for IoT hardware and software design, including machine learning<br /> * Unconventional computing using oscillators<br /> * Perturbation Biology Modeling<br /> <br /> <br /> Some project descriptions are as follows.<br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]], [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> <br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, Ceyhun Kayan, Sief Atari (quit), [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (1232164, [[2008629]]), Mosis<br /> <br /> Collaborator(s): Kapil Dandekar (Wireless Communication Systems, Co-PI)<br /> <br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, [[Leo Filippini]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Emre Salman SUNY-Stony Brook, Diane Lim (Penn School of Medicine), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).<br /> <br /> <br /> == Unconventional Computing using oscillators==<br /> <br /> Unconventional Computing using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> <br /> Ph.D. Student(s): [[Nicholas Sica]], [[Yilmaz Gonul]]<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Ragh Kuttappa (Intel), Vinayak Honkote (Intel)<br /> <br /> == Perturbation Biology Modeling==<br /> <br /> This research uses algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.<br /> <br /> <br /> <br /> Ph.D. Student(s): Ceyhun Kayan<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Anil Korkut (MD Anderson)<br /> <br /> <br /> = Previous Projects = <br /> <br /> <br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Leo Filippini]] (graduated), [[Can Sitik]] (graduated)<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Collaborator(s): Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]] (graduated), [[Can Sitik]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> <br /> == CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> <br /> Check our Software Release: [[SynchroTrace]]<br /> <br /> <br /> <br /> Ph.D. Student(s): [[Karthik Sangaiah]] (graduated), [[Michael Lui]], [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Mark Hempstead, Tufts (Computer Architecture)<br /> <br /> <br /> == Energy Efficient Computing with OptoElectronics==<br /> <br /> In order to achieve energy efficient computing for systems ranging from datacenters down to mobile electronics, novel devices, techniques, and methodologies are necessary to reduce the terawatts of power consumed by computational devices. We are proposing an effort to bring together researchers from all levels of the device to systems hierarchy (Devices -&gt; Circuits -&gt; Architecture -&gt; Systems -&gt; Data Center) in a vertically integrated approach addressing the (energy) challenges of future computing devices. Our vision is to build upon novel optoelectronic devices capable of computing a bit while consuming attojoules (10E-18 J) of energy, and progress to energy efficient techniques and methodologies for data centers that consume terawatts of power from the electrical grid. Energy efficient innovations at the circuits, systems/interconnect, architecture, and server/mobile/datacenter platform level have the potential to significantly reduce overall power consumption and address this grand challenge in energy needs. Our team is to leverage the energy efficiency of novel optoelectronic elements, and focus research efforts on reducing the total power consumption of electronic devices through energy efficient techniques and methodologies for IC chips, devices, and ultimately data centers that consume terawatts of power from the electrical grid. <br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Bahram Nabet (Photonics), Ioannis Savidis (Circuits and Systems), Naga Kandasamy (HPC), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).<br /> <br /> <br /> <br /> == GPU System Co-design ==<br /> <br /> Similar to CMP-NoC Design challenges, the co-design of hardware and software on GPU systems is explored. Platform independent dependencies of threads are analyzed on GPUs, leading to the analysis of software and hardware co-design principles.<br /> <br /> Ph.D. Student(s): [[Michael Lui]], [[Karthik Sangaiah]] (graduated)<br /> <br /> Sponsor(s): Samsung GRO <br /> <br /> Collaborator(s): Mark Hempstead (Computer Architecture)<br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=7708 2025-02-05T15:03:24Z

<p>Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */</p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> #''Unconventional Computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.<br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> &lt;!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. --&gt;<br /> # ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> [[Sief Atari]]<br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Ceyhun Kayan]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=7707 2025-02-05T15:02:58Z

<p>Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */</p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> #''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.<br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> &lt;!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. --&gt;<br /> # ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> [[Sief Atari]]<br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Ceyhun Kayan]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=7706 2025-02-05T15:02:40Z

<p>Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */</p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> #''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # &quot;Perturbation Biology Modeling&quot;, using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.<br /> <br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> &lt;!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. --&gt;<br /> # ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> [[Sief Atari]]<br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Ceyhun Kayan]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=7705 2025-02-05T15:00:20Z

<p>Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */</p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> #''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> &lt;!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. --&gt;<br /> # ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> [[Sief Atari]]<br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Ceyhun Kayan]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Main_Page&diff=7704 2025-02-05T14:59:44Z

<p>Taskin: /* Drexel VLSI and Architecture Laboratory (VANDAL) */</p> <hr /> <div><br /> __NOTOC__<br /> <br /> [[File:VANDAL.png|right|super|200px]]<br /> <br /> == Drexel VLSI and Algorithms Laboratory (VANDAL) ==<br /> <br /> Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. &lt;!--Grand research goals are:<br /> <br /> <br /> # ''Design of Smart Cities and Homes''<br /> # ''Architectures for Security and Energy Efficiency of Cyber Physical Systems and IoT devices''<br /> # ''Architectures and Efficient Design Methods for Future Healthcare''<br /> <br /> --&gt;<br /> <br /> <br /> <br /> VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:<br /> <br /> <br /> # ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.<br /> # ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> # &quot;Unconventional computing&quot; using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.<br /> # ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.<br /> # ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.<br /> # ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).<br /> &lt;!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. --&gt;<br /> # ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.<br /> <br /> <br /> <br /> [http://www.drexel.edu Drexel University]<br /> <br /> [http://www.ece.drexel.edu Department of Electrical and Computer Engineering]<br /> <br /> [http://maps.google.com/maps?f=q&amp;amp;source=s_q&amp;amp;hl=en&amp;amp;geocode=&amp;amp;q=3141+chestnut+Street+19104&amp;amp;sll=37.649034,-95.712891&amp;amp;sspn=37.558981,49.21875&amp;amp;ie=UTF8&amp;amp;ll=39.963241,-75.181932&amp;amp;spn=0.008948,0.012016&amp;amp;z=14&amp;amp;iwloc=A&amp;amp 3141 Chestnut Street (map) ]<br /> <br /> 324 Bossone Research Center<br /> <br /> Philadelphia, PA 19104<br /> <br /> &lt;!-- Comments out<br /> <br /> = ''' PhD student Research Assistantship positions are available ''' = <br /> <br /> Multiple open positions to be filled in Winter/Spring/Fall 2022. Seeking interest in some (not all) of the following areas:<br /> <br /> * VLSI<br /> * computer architecture<br /> * programming<br /> * optimization<br /> * networking<br /> * integrated circuits<br /> <br /> Apply through the Drexel University website: [http://drexel.edu/grad/ Drexel Admissions]<br /> <br /> <br /> --&gt;<br /> <br /> ----<br /> <br /> == [[People]] ==<br /> <br /> === Faculty ===<br /> <br /> [[Baris Taskin| Baris Taskin (Biography, CV, Contact)]] <br /> <br /> === Ph.D. students ===<br /> <br /> [[Sief Atari]]<br /> <br /> [[Yilmaz Gonul]]<br /> <br /> [[Ceyhun Kayan]]<br /> <br /> [[Scott Lerner]]<br /> <br /> [[Michael Lui]]<br /> <br /> [[Nicholas Sica]]<br /> <br /> === Other researchers ===<br /> <br /> See [[People]]<br /> <br /> == [[Research]] ==<br /> <br /> <br /> &lt;!--<br /> [[Research#Resonant Clocking Technologies|Resonant Clocking Technologies]]<br /> <br /> [[Research#CMP-NoC Co-design|CMP-NoC Co-design]]<br /> <br /> [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]]<br /> <br /> [[Research#Wireless On-Chip Interconnects|Wireless On-Chip Interconnects]]<br /> <br /> [[Research#Clock Tree/Mesh Synthesis|Clock Tree/Mesh Synthesis]]<br /> <br /> [[Research#Ultra Low-Power Adiabatic Circuit Design|Ultra Low-Power Adiabatic Circuit Design]]<br /> <br /> [[Research#Energy Efficient Computing with OptoElectronics|Energy Efficient Computing with OptoElectronics]]<br /> <br /> --&gt;<br /> <br /> == [[Publications]] ==<br /> <br /> == [[Software]] ==<br /> <br /> [https://github.com/VANDAL Github]<br /> <br /> [[Software#SynchroTrace|SynchroTrace]]<br /> <br /> &lt;!--[[Software#SLECTS|SLECTS]]<br /> <br /> [[Software#RotarySynthesis|RotarySynthesis]]<br /> <br /> --&gt;<br /> == [[Seminars]] ==<br /> <br /> == [[Tutorials]] ==<br /> <br /> == [[Teaching]] ==<br /> <br /> == [[News/Events]] ==</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=7165 2024-11-18T17:38:58Z

<p>Taskin: </p> <hr /> <div>&lt;!-- [[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin's quintessential professor's outdated photo 2005]]|25px]] --&gt;<br /> [[File:BarisTaskin05small.jpg|right|border|frame|[[2023 photo]]|x1px]]<br /> <br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering Department at Drexel University, Philadelphia, PA in 2005, where currently he is a Professor. Between 2003-2004, he was a PhD intern engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015. He is an associate editor for JCSC and Elsevier's Microelectronics. He served as the General Chair for SLIP 2016 and GLVLSI 2019, as the Chair for IEEE CEDA Pennsylvania Chapter (2018-current), and the Chair of the IEEE Circuits and Systems Society's VLSI and Systems Applications Technical Committee (IEEE CASS VSA-TC) (2018-2020).<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Professor (2016-present)<br /> ; Associate Professor (2011-2016)<br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Ph.D. Intern Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> [http://vlsi.ece.drexel.edu/images/8/81/Taskin_CV.pdf CV (September 2024)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> '''Campus Location:'''<br /> &lt;br&gt; Office: Bossone Building 401<br /> &lt;br&gt; Lab: Bossone Building 405<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=7164 2024-11-18T17:38:31Z

<p>Taskin: </p> <hr /> <div>% [[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin's quintessential professor's outdated photo 2005]]|25px]]<br /> [[File:BarisTaskin05small.jpg|right|border|frame|[[2023 photo]]|x1px]]<br /> <br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering Department at Drexel University, Philadelphia, PA in 2005, where currently he is a Professor. Between 2003-2004, he was a PhD intern engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015. He is an associate editor for JCSC and Elsevier's Microelectronics. He served as the General Chair for SLIP 2016 and GLVLSI 2019, as the Chair for IEEE CEDA Pennsylvania Chapter (2018-current), and the Chair of the IEEE Circuits and Systems Society's VLSI and Systems Applications Technical Committee (IEEE CASS VSA-TC) (2018-2020).<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Professor (2016-present)<br /> ; Associate Professor (2011-2016)<br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Ph.D. Intern Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> [http://vlsi.ece.drexel.edu/images/8/81/Taskin_CV.pdf CV (September 2024)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> '''Campus Location:'''<br /> &lt;br&gt; Office: Bossone Building 401<br /> &lt;br&gt; Lab: Bossone Building 405<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=7163 2024-10-15T13:44:03Z

<p>Taskin: /* Publications */</p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkiye)<br /> <br /> Junghoon Oh Ph.D. (visiting PhD student co-author on research products, Japan Institute of Technology, advised by Prof. Mineo Kaneko)<br /> <br /> Vinayak Honkote, Ph.D., Ragh Kuttappa, Intel, OR (co-authors on research products)<br /> <br /> == Publications ==<br /> Publications list is updated 2024/10. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> * Yilmaz Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Miner Kaneko, Baris Taskin, &quot;Design Automation for Charge Recovery Logic&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin, &quot;High Speed Phase-Based Computing&quot;, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Undergraduate summer research, STAR freshman program, Jonah Taylor<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 10/2024</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=7162 2024-10-15T13:41:51Z

<p>Taskin: /* Educational activities */</p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkiye)<br /> <br /> Junghoon Oh Ph.D. (visiting PhD student co-author on research products, Japan Institute of Technology, advised by Prof. Mineo Kaneko)<br /> <br /> Vinayak Honkote, Ph.D., Ragh Kuttappa, Intel, OR (co-authors on research products)<br /> <br /> == Publications ==<br /> Publications list is updated 2022/10. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Undergraduate summer research, STAR freshman program, Jonah Taylor<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 10/2024</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=7161 2024-10-15T13:41:08Z

<p>Taskin: /* Collaborators */</p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkiye)<br /> <br /> Junghoon Oh Ph.D. (visiting PhD student co-author on research products, Japan Institute of Technology, advised by Prof. Mineo Kaneko)<br /> <br /> Vinayak Honkote, Ph.D., Ragh Kuttappa, Intel, OR (co-authors on research products)<br /> <br /> == Publications ==<br /> Publications list is updated 2022/10. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 10/2024</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=7160 2024-10-15T13:40:58Z

<p>Taskin: /* Collaborators */</p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkey)<br /> <br /> Junghoon Oh Ph.D. (visiting PhD student co-author on research products, Japan Institute of Technology, advised by Prof. Mineo Kaneko)<br /> <br /> Vinayak Honkote, Ph.D., Ragh Kuttappa, Intel, OR (co-authors on research products)<br /> <br /> == Publications ==<br /> Publications list is updated 2022/10. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 10/2024</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Research&diff=7159 2024-10-15T13:37:56Z

<p>Taskin: /* Wireless On-Chip Interconnects */</p> <hr /> <div>Drexel VANDAL consists of a research group of computer engineers and electrical engineers tackling big engineering problems of building sophisticated systems. Some of the projects are in:<br /> * Exa-scale computing systems<br /> * Smart energy/Smart home systems<br /> * IoT processor design<br /> * Bio-Implantable systems<br /> * 5G communication systems<br /> * Algorithms and software for IoT hardware and software design, including machine learning<br /> <br /> <br /> <br /> Some project descriptions are as follows.<br /> <br /> == Resonant Clocking Technologies ==<br /> <br /> Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.<br /> <br /> With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.<br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]], [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis<br /> <br /> == CMP-NoC Co-design ==<br /> <br /> The advent of multi-core architectures has increased the popularity of chip multi-processors (CMP) and the use of networks-on-chip (NoCs) as a fabric interconnecting cores in high performance computers. Traditionally, the evaluation of the NoCs design space has been carried out with traces, and a less used alternative being full system simulations. Traces do not capture the message dependencies in real applications which makes replaying a trace less accurate than a full system simulation. While full system simulations provide high accuracy, they are hindered by extremely long run times and limitations in the number of cores. Previous attempts at generating traces with message dependencies involve the generation of traces through full-system simulations which are platform dependent and extremely difficult especially for massive multi-core systems (i.e hundreds of cores).<br /> <br /> In this work we present a platform independent, dependency tracked event-based NoC evaluation methodology. Since the events track dependencies between multiple threads, the presented methodology is capable of replaying messages across the network in the correct order which ensures accuracy, while it does not require simulating the functionality of a microprocessor, like full system simulators do. In addition, the presented framework can be scaled easily to evaluate future NoCs for massive multi-core CMPs comprising of hundreds of nodes. The methodology is used to explore the design space in the CMP-NoC co-design process.<br /> <br /> <br /> Check our Software Release: [[SynchroTrace]]<br /> <br /> <br /> <br /> Ph.D. Student(s): Sief Atari, [[Karthik Sangaiah]] (graduated), [[Michael Lui]], [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Mark Hempstead, Tufts (Computer Architecture)<br /> <br /> == Design and Automation of Low Swing Clocking ==<br /> <br /> Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]], [[Leo Filippini]] (graduated), [[Can Sitik]] (graduated)<br /> <br /> Sponsor(s): Semiconductor Research Corporation<br /> <br /> Collaborator(s): Emre Salman, SUNY-Stony Brook (Circuits and Systems)<br /> <br /> == Wireless On-Chip Interconnects ==<br /> <br /> Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.<br /> <br /> In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.<br /> <br /> Also see our article titled [[WirelessInterconnect|&quot;What is Wireless Interconnect?&quot;]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, Ceyhun Kayan, Sief Atari (quit), [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)<br /> <br /> Sponsor(s): National Science Foundation (1232164, [[2008629]]), Mosis<br /> <br /> Collaborator(s): Kapil Dandekar (Wireless Communication Systems, Co-PI)<br /> <br /> == Clock Tree/Mesh Synthesis ==<br /> <br /> In this research, the utilization of computing power to improve an essential step of integrated circuit (IC) physical design flow, clock network design, is investigated. Clock network design entails a series of computationally intensive, large-scale design and optimization tasks. Automation for conventional, zero skew, buffered clock trees is common. However, high performance clock tree design remains a tedious task with increasing requirements for higher speed through skew scheduling, variation-awareness and constrained power budgets. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research.<br /> <br /> In the traditional integrated circuit design flow, the placement and clock network synthesis stages are performed sequentially. It is desirable to combine the placement and clock network synthesis stages to provide a better physical design. In this project, the integration of placement and clock network synthesis is investigated for the purpose of reducing clock power dissipation. Moreover, various types of novel clock distribution architectures are studied.<br /> <br /> Ph.D. Student(s): [[Scott Lerner]], [[Can Sitik]] (graduated), [[Jianchao Lu]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> == Ultra Low-Power Adiabatic Circuit Design ==<br /> <br /> Adiabatic switching provides the preservation of energy by circulating the switching energy back into the circuit. The recirculation of energy has significantly limited the frequency of operation. The frequency of operation is dictated by a synchronizing clock signal called the power-clock, which also acts as the power source for the adiabatic logic. Some adiabatic logic families, however, require multiple phases of the power-clock for pipelined operation (alternatively, logic pipelining can be sacrificed). Also impacting the adaptation of adiabatic logic is the recovery path resistance and its impact on the Q of the LC resonator impeding the quality of synchronization and the power recovery. Consequently, adiabatic circuit families have faced difficulties in being adapted in IC design due to:<br /> 1. The low switching frequency of the power-clock signals,<br /> 2. The difficulty in logic pipelining, primarily due to the power dissipation required to provide the complex clocking schemes with multiple phases.<br /> <br /> In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.<br /> <br /> Ph.D. Student(s): Yilmaz Gonul, [[Leo Filippini]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Emre Salman SUNY-Stony Brook, Diane Lim (Penn School of Medicine), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).<br /> <br /> == Energy Efficient Computing with OptoElectronics==<br /> <br /> In order to achieve energy efficient computing for systems ranging from datacenters down to mobile electronics, novel devices, techniques, and methodologies are necessary to reduce the terawatts of power consumed by computational devices. We are proposing an effort to bring together researchers from all levels of the device to systems hierarchy (Devices -&gt; Circuits -&gt; Architecture -&gt; Systems -&gt; Data Center) in a vertically integrated approach addressing the (energy) challenges of future computing devices. Our vision is to build upon novel optoelectronic devices capable of computing a bit while consuming attojoules (10E-18 J) of energy, and progress to energy efficient techniques and methodologies for data centers that consume terawatts of power from the electrical grid. Energy efficient innovations at the circuits, systems/interconnect, architecture, and server/mobile/datacenter platform level have the potential to significantly reduce overall power consumption and address this grand challenge in energy needs. Our team is to leverage the energy efficiency of novel optoelectronic elements, and focus research efforts on reducing the total power consumption of electronic devices through energy efficient techniques and methodologies for IC chips, devices, and ultimately data centers that consume terawatts of power from the electrical grid. <br /> <br /> Ph.D. Student(s): [[Ragh Kuttappa]] (graduated)<br /> <br /> Sponsor(s): None<br /> <br /> Collaborator(s): Bahram Nabet (Photonics), Ioannis Savidis (Circuits and Systems), Naga Kandasamy (HPC), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).<br /> <br /> = Previous Projects = <br /> <br /> <br /> == GPU System Co-design ==<br /> <br /> Similar to CMP-NoC Design challenges, the co-design of hardware and software on GPU systems is explored. Platform independent dependencies of threads are analyzed on GPUs, leading to the analysis of software and hardware co-design principles.<br /> <br /> Ph.D. Student(s): [[Michael Lui]], [[Karthik Sangaiah]] (graduated)<br /> <br /> Sponsor(s): Samsung GRO <br /> <br /> Collaborator(s): Mark Hempstead (Computer Architecture)<br /> <br /> == Clock Skew Scheduling ==<br /> <br /> Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to achieve high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design principle is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.<br /> <br /> In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew scheduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to improve timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.<br /> <br /> Ph.D. Student(s): [[Jianchao Lu]] (graduated)<br /> <br /> == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==<br /> <br /> It is expected that the physical barrier in the nanoscale implementation of CMOS devices will soon be reached. The development of next generation computation systems will stem from the exploration of nanoscale materials and biological systems. Properties and applications of several nanoscale technologies, such as Quantum-dot Cellular Automata (QCA) investigated in this work, are being explored intensively. Basic design methods and simulators have been developed to show the potential of QCA technology in meeting future computation needs. What is missing in the current agenda of QCA research are studies on layout optimization and system-level architecture design. The challenge in performing these studies is the necessity to address the high levels of pipelining, parallelism, and fault-tolerance required for high performance operation of QCA systems.<br /> <br /> The objective of the proposed research is to investigate fault-tolerant QCA architectures using advanced clocking schemes for practical implementation of QCA-based nanocomputers. Towards this end, essential circuit components for such computers and system-level integration of these components will be investigated. In the project, the emphasis is on novel circuit architectures and clocking schemes to perform computations with this emerging technology. Manufacturing challenges will be addressed to capture the fault-tolerance properties for architecture design.<br /> <br /> Ph.D. Student(s): None<br /> <br /> ----</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=7158 2024-10-15T13:32:33Z

<p>Taskin: </p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkey)<br /> <br /> == Publications ==<br /> Publications list is updated 2022/10. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 10/2024</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=2008629&diff=7157 2024-10-15T13:29:16Z

<p>Taskin: </p> <hr /> <div><br /> == CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems==<br /> <br /> <br /> == Award information ==<br /> <br /> Award Number:2008629<br /> <br /> Project Title:CNS Core: Small: Wireless Interconnect Networks on Multi-Die Systems<br /> <br /> Report Type: Annual Project Report<br /> <br /> PI:BarisTaskin<br /> <br /> Awardee:Drexel University <br /> <br /> [https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008629&amp;HistoricalAwards=false NSF award page]<br /> <br /> <br /> == Synopsis ==<br /> <br /> Advances in semiconductor technology have enabled sophisticated computing systems to be integrated in small form-factor devices that are widely used in not only in computers, but in consumer electronics such as cellphones and have enabled a host of applications, such as the internet-of-things, wearable electronics, portable medical devices, etc. The integration of multiple computing and storage units in a single semiconductor device necessitates the scaling of networking science, typically developed for constraints between computers (such as the internet), down to a single-chip level, in order to enable efficient communication between on-chip elements. This enables data-center-like operation on an individual chip populated with hundreds of processing elements, with computation capabilities that are equivalent to a network of computers, but with much improved portability, cost-effectiveness and energy-efficiency. Such advancements are important to maintain US leadership of the computing, networking and semiconductor industries, as well as improving the connectivity of national human resources and the physical infrastructure.<br /> <br /> This project investigates computing system, VLSI, antenna design and networking principles for the integration of a novel Through-Silicon-Via-Antenna (TVSA)-based wireless network system into semiconductor devices packaged in the form factor of heterogeneous multi-die integration. The proposed wireless network for multi-die systems aims to create a scalable, reliable, and efficient network interconnect for current and emerging industry-standard multi-die processors. Through-Silicon-Via-Antennas are highly suited for on-chip wireless communication at minuscule footprints. This project focuses on the following tasks: (a) design and characterization of on-package TSVA; (b) wireless propagation modelling and channel characterization for multi-die systems using a Software Defined Radio (SDR) prototyping testbed; and (c) interconnect network system design by considering routing, latency, and throughput via cycle-accurate system-level simulations.<br /> <br /> This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.<br /> <br /> <br /> == Personnel ==<br /> <br /> ===Faculty ===<br /> <br /> Prof. Baris Taskin (PI, Drexel University)<br /> <br /> Prof. Kapil Dandekar (Co-PI, Drexel University)<br /> <br /> === PhD Students &amp; Post-Pocs ===<br /> <br /> Vasil Pano, PhD. (graduated, @ Intel)<br /> <br /> Anim Kyei, Ph.D. (post-doc @ Drexel)<br /> <br /> Ragh Kuttappa, Ph.D. (graduated, @ Intel)<br /> <br /> Scott Lerner, Ph.D. (graduated, @ Intel)<br /> <br /> Sief Atari (quit program)<br /> <br /> Yilmaz Gonul (continuing Ph.D.)<br /> <br /> Ceyhun Kayan (continuing Ph.D.)<br /> <br /> === MS Students ===<br /> Angela Wei., MS (graduated)<br /> <br /> === Collaborators===<br /> Prof. Ibrahim Tekin (Visiting faculty contributor, Sabanci University, Turkey)<br /> <br /> == Publications ==<br /> Publications list is updated 2022/10. For updates, see [[Publications]]<br /> <br /> === Conference and Journals ===<br /> <br /> * A. Ganguly, S. Abadal, I. Thakkar, N. E. Jerger, M. Riedel, M. Babaie, R. Balasubramonian, A. Sebastian, S. Pasricha, B. Taskin, A. Ganguly et al., &quot;Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion,&quot; ''IEEE Micro'', vol. 42, no. 3, pp. 40-49, 1 May-June 2022, doi: 10.1109/MM.2022.3150684.<br /> <br /> * Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, &quot;Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems&quot;, ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636--1645, April 2021. [https://ieeexplore.ieee.org/document/9360308 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV Antennas for Multi-Band Wireless Communication&quot;, ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;TSV-based Antenna for On-Chip Wireless Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]<br /> <br /> * Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, &quot;Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication&quot;, ''IET Microwaves, Antennas &amp; Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]<br /> <br /> * Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, &quot;Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]<br /> <br /> * Vasil Pano, Ragh Kuttappa, and Baris Taskin, &quot;3D NoCs with Active Interposer for Multi-Die Systems&quot;, ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]<br /> <br /> * Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, &quot;In-Package Wireless Communication with TSV-based Antenna&quot;, ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]<br /> <br /> * Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, &quot;mmWave Antenna Gain Switching to Mitigate Indoor Blockage&quot;, ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]<br /> <br /> * Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, &quot;Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]<br /> <br /> * Scott Lerner, Vasil Pano, and Baris Taskin, &quot;NoC Router Lifetime Improvement using Per-Port Router Utilization&quot;, ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]<br /> <br /> === Thesis and Dissertations ===<br /> <br /> * Angela Wei, M.S. thesis, &quot;Novel Wireless Non-Uniform Multi-Die Systems&quot;, 2021<br /> <br /> * Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019<br /> <br /> <br /> == Code ==<br /> <br /> Code release for wireless multi-die system simulations:<br /> <br /> https://github.com/aw868/new_aw868_gem5<br /> <br /> <br /> == Educational activities ==<br /> <br /> Independent research projects at the graduate level for Angela Wei<br /> <br /> Post-doc mentoring by PIs<br /> <br /> Post-Doc career development by advising MS level graduate research and REU<br /> <br /> <br /> == Outreach and other broader impact outcomes ==<br /> <br /> Institution Open Houses for high school students<br /> <br /> Panel discussion and position paper on wireless interconnects<br /> <br /> Vertically Integrated Projects - disrupted by Covid break<br /> <br /> Presentation of conference research work on video, released and available by conference sponsors (some publicly available for limited time)<br /> <br /> Invention disclosure: https://patents.google.com/patent/US11329362B2/en?oq=US11329362B2<br /> <br /> <br /> edited 10/20222</div>

Taskin https://research.coe.drexel.edu/ece/vlsi/index.php?title=Baris_Taskin&diff=7155 2024-09-21T16:11:44Z

<p>Taskin: /* Curriculum Vitae */</p> <hr /> <div>[[File:Baris-Taskin.jpg|right|border|frame|[[Baris Taskin's quintessential professor's outdated photo 2005]]|25px]]<br /> [[File:BarisTaskin05small.jpg|right|border|frame|[[2023 photo]]|x1px]]<br /> <br /> <br /> == Biography ==<br /> <br /> Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He also received the minor program diploma in operations research from Middle East Technical University, Ankara, Turkey, in 2000, and the certificate in system-on-chip (SOC) design from Pittsburgh Digital Greenhouse [currently called The Technology Collaborative (TTC)], Pittsburgh, PA (in cooperation with the University of Pittsburgh, the Pennsylvania State University and Carnegie Mellon University), in 2003.<br /> <br /> He joined the Electrical and Computer Engineering Department at Drexel University, Philadelphia, PA in 2005, where currently he is a Professor. Between 2003-2004, he was a PhD intern engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is an &quot;A. Richard Newton Award&quot; winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015. He is an associate editor for JCSC and Elsevier's Microelectronics. He served as the General Chair for SLIP 2016 and GLVLSI 2019, as the Chair for IEEE CEDA Pennsylvania Chapter (2018-current), and the Chair of the IEEE Circuits and Systems Society's VLSI and Systems Applications Technical Committee (IEEE CASS VSA-TC) (2018-2020).<br /> <br /> == Education ==<br /> <br /> ; Ph.D. in Electrical Engineering, 2005<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; M.S. in Electrical Engineering, 2003<br /> : University of Pittsburgh, Pittsburgh, PA<br /> <br /> ; B.S. in Electrical and Electronics Engineering, 2000<br /> ; Minor in Operations Research, 2000<br /> : Middle East Technical University (METU), Ankara, Turkey<br /> <br /> == Experience ==<br /> <br /> ; Professor (2016-present)<br /> ; Associate Professor (2011-2016)<br /> ; Assistant Professor (2005-2011)<br /> : Department of Electrical and Computer Engineering<br /> : Drexel University, Philadelphia, PA<br /> <br /> ; Ph.D. Intern Engineer (09/2003 - 06/2004)<br /> : Multigig Inc., Scotts Valley, CA<br /> <br /> == Curriculum Vitae ==<br /> <br /> <br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/8/81/Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> &lt;!-- [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/archive/8/81/20100720020839%21Taskin_CV.pdf CV (Jul 2010)] --&gt;<br /> <br /> &lt;!-- [[media:Taskin_CV.pdf|CV (October 2010)]] --&gt;<br /> <br /> [http://vlsi.ece.drexel.edu/images/8/81/Taskin_CV.pdf CV (September 2024)]<br /> <br /> == Contact Info ==<br /> <br /> '''Mail Address:'''<br /> &lt;br&gt;3141 Chestnut Street<br /> &lt;br&gt;ECE Department<br /> &lt;br&gt;Drexel University<br /> &lt;br&gt;Philadelphia, PA 19104<br /> <br /> '''Campus Location:'''<br /> &lt;br&gt; Office: Bossone Building 401<br /> &lt;br&gt; Lab: Bossone Building 405<br /> <br /> &lt;br&gt;Phone: (215) 895-5972<br /> &lt;br&gt;Fax: (215) 895-1695<br /> <br /> &lt;br&gt; Email: [[File:taskinemail.png|200px|mailto:taskin@coe.drexel.edu]]</div>

Taskin