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2024-07-12T17:45:35Z

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Vasil Pano

2023-05-10T13:41:53Z

Vasil: /* Contact Information */

Vasil Pano

2023-05-10T13:41:18Z

Vasil: /* Publications */

Vasil Pano

2023-05-10T13:37:40Z

Vasil: /* Resume - Curriculum Vitae */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Electrical Engineering, 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (May 2023)]]

== Publications ==
====Journal Publications====
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and '''Vasil Pano''', "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021.
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, '''Vasil Pano''', and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

File:Vasil Pano Resume.pdf

2023-05-10T13:37:28Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

File:Vasil Pano Resume.pdf

2021-03-11T14:55:05Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

File:Vasil Pano Resume.pdf

2021-03-07T20:47:24Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

File:Vasil Pano Resume.pdf

2021-03-06T15:32:46Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

File:Vasil Pano Resume.pdf

2021-03-05T18:46:38Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

File:Vasil Pano Resume.pdf

2021-03-04T18:16:05Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

File:Vasil Pano Resume.pdf

2021-03-04T16:06:36Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

SynchroTrace

2021-03-04T05:57:37Z

Vasil:

== SynchroTrace ==

SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of CMPs. The first step, capturing synchronization-aware traces of multi-threaded applications, leverages an extension of prior work (Sigil). The second step represents an timing model for replaying the synchronization-aware traces into external architecture models. Together, these two stages represent ‘SynchroTrace’.

To leverage this methodology for design space exploration, we have developed a prototype of SynchroTrace integrated into the cache and NoC simulators of Gem5 (Ruby and Garnet, respectively). We defined this prototype integration as the SynchroTrace Simulation Framework, and the code for this framework is available below.

=Overview:=

The capture tool is built from Sigil, which leverages the Valgrind dynamic binary instrumentation tool. The processed instructions from the native multi-threaded applications are abstracted into (3) events: Computation (Work performed local to a thread), Communication (Read/Write dependencies between threads), and Synchronization (embedded pthread calls for each thread). These events form a trace for each individual thread, so that these threads may progress in parallel when replaying the traces.

Computation Event (indicated by the $ and * symbols):
[Thread ID, Event Number, Number of Integer Operations, Number of Floating Point Operations, Number of Memory Reads, Number of Memory Writes $ Range of Unique Addresses Written * Range of Unique Addresses Read]

Communication Event (indicated by the # symbol):
[Thread ID, Event Number # Producer Thread ID, Produce Event Number, Range of Unique Addresses Read]

Synchronization Event (indicated by the pth_th and ^ symbol):
[Thread ID, Event Number, pth_ty: Pthread Call Type ^ Address of Synchronization Structure]

=Replay Model:=

Traces are fed into the replay timing model, which acts as an interface into the external architecture models.

[[File:ST_Capture_Replay.png| SynchroTrace Capture/Replay Flow]]

The Replay portion of SynchroTrace is comprised of 4 entities:

Trace Translator – Converts the traces into an event form to be fed into the timing model.

Event Queue Manager – Centralized event queue that manages the timing of thread progression based on the three types of events. The Event Queue Manager also handles the timing for when to send memory requests to the external cache simulator.

Thread Scheduler – Creates and maintains the thread state. The Thread Scheduler includes a light-weight swapping mechanism to allow for multiple threads to run on a core. The scheduler also handles the appropriate synchronization actions.

Memory Request Manager – Interface to the external architecture models. For the SynchroTrace Simulation Framework, the memory request manager packages the memory requests into requests for Ruby.

=Getting SynchroTrace:=

The SynchroTrace Simulation Framework is accessible through GitHub at: [https://github.com/VANDAL/SynchroTrace-gem5 git.io/synchrotrace]

Currently, there is only a repository for playing the synchronization-aware traces into the external cache and NoC models (Ruby and Garnet). We’ve included a few sample traces to test and explore this code-base. We are currently prepping the capture tool for release very soon.

The SynchroTrace publication can be found [[media:SynchroTrace.pdf‎|here]].

= Dependencies:=

The SynchroTrace Simulation Framework is integrated into Gem5′s cache and NoC simulators (Ruby and Garnet). Thus, SynchroTrace’s dependencies are based on Gem5′s dependencies. Please refer to http://www.gem5.org/Dependencies for more information.

SynchroTrace has been tested on Intel Xeon E5-based machines, running either RedHat Enterprise Linux 5, Centos 6, or Ubuntu 12.x operating systems. We have generated traces for PARSEC and Splash-2 benchmarks (up to 64 threads reliably) and ran them through our SynchroTrace Simulation Framework.

= Running the first time:=

Please follow the included Readme to compile SynchroTrace and run the sample traces for the first time.

SynchroTrace

2021-03-04T05:56:48Z

Vasil: /* Also available at */

File:Vasil Pano Resume.pdf

2021-03-04T05:22:33Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

Vasil Pano

2021-03-04T05:21:50Z

Vasil: /* Resume - Curriculum Vitae */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Electrical Engineering, 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (March 2021)]]

== Publications ==
====Journal Publications====
# Ragh Kuttappa, Baris Taskin, Scott Lerner, and '''Vasil Pano''', "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted February 2021.
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, '''Vasil Pano''', and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

News/Events

2021-03-03T02:54:33Z

Vasil:

* CEDA sponsored Drexel Computer Engineering Graduate Symposium program is On for Winter 2020.

* Dr. Taskin is delivering the keynote "On-Chip Wireless Interconnect Paradigm" at [http://www.nocarc.org 12th International Workshop on Network on Chip Architectures (NoCARC) 2019], held in conjuction with MICRO 2019 in Columbus Ohio.
<gallery>
File:NoCARC19Keynote.png
</gallery>

* Mike Lui is interning at Facebook Fall 2019.

* Scott Lerner is interning at Intel Summer/Fall 2019.

* Vasil is now Dr. Vasil Pano, Summer 2019.

* Leo is now Dr. Leo Filippini, Spring 2019.

* Our resonant clock team RotaSyn participated in National Science Foundation I-Corps Short Course at Drexel University organized by Upstate NY I-Corps Node, March 2019.
<gallery>
File:Rotasyn-Session5Cover.png
</gallery>

* CEDA sponsored Drexel Computer Engineering Graduate Symposium program is On for Winter 2019.

* Scott Lerner received the Koerner Family Award in 2019.

* Dr. Taskin is the General Chair for ACM GLSVLSI 2019 in Tysons Corner, VA.
<gallery>
File:GLSVLSI19Chair.png
</gallery>

* Dr. Taskin elected the chair of [http://ieee-cas.org/community/technical-committees/vlsi-systems-applications-technical-committee-vsatc IEEE Circuits and Systems Society's (CASS) Technical Committee on VLSI Systems and Applications (CAS VSA-TC)], 2018-2020.
<gallery>
File:VSATCChair.png
</gallery>

* Vasil Pano received the Nihat Bilgutay Award in 2018.

* Mike Lui received the Koerner Family Award in 2018.

* Karthik Sangaiah, Scott Lerner, and Ragh Kuttappa receive the Weggel Family Fellowship in 2018.

* Scott Lerner, Vasil Pano and Baris Taskin won the first place at the 10th Annual Drexel IEEE Graduate Symposium poster competition for their work on "NoC Router Lifetime Improvement Using Per-Port Router Utilization", accepted at IEEE International Symposium on Circuits and Systems (ISCAS).

* Completed CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2018.

* Dr. Taskin is the TPC co-chair for ACM GLSVLSI 2018 in Chicago, IL.

* Granted United States Patent No. 9,773,079, ``Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits'', Inventors: Taskin and Sitik, 2017

*Granted United States Patent No. 9,484,896, ``Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling'', Inventors: Taskin and Teng, 2017

* Scott Lerner, Vasil Pano, and Leo Filippini receive ECE awards in 2017.

* Mike Lui and Kartik Sangaiah will give a tutorial on "Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation" @ International Symposium on Workload Characterization (IISWC), 2016.

* Can Sitik received Honorable mention for the Outstanding Dissertation Award at Drexel College of Engineering graduation in 2016.

* Scott received the Frank & Agnes Seaman fellowship from the Department of Electrical & Computer Engineering, Drexel University in 2016.

* Leo received the Carleone fellowship from the Department of Electrical & Computer Engineering, Drexel University in 2016.

* Vasil Pano and Scott Lerner recipients of the A. Richard Newton Young Student Fellow Program award for the Design Automation Conference in Austin, TX in 2016.

* Junghoon Oh, a PhD student from JAIST, Japan, joins the lab as a visiting researcher for 2016.

* IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Spring 2016.
<gallery>
File:2016_Sp_symposiaFlyer.png
</gallery>

* The first IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium talk for Spring 2016.
<gallery>
File:2016_Sp_symposium_01.png
</gallery>

* IEEE CEDA sponsored Drexel Computer Engineering Graduate Symposium program for Winter 2016.
<gallery>
File:symposia-winterFlyer16.png
</gallery>

* Prof. Taskin is the General Chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016 [http://sliponline.org]

* Dr. Taskin received the Outstanding Research award from the Drexel ECE Department in 2015.

* Dr. Taskin started and will serve as the treasurer of the IEEE Central Pennsylvania, Pittsburgh, Philadelphia Joint Sections Council of Electronic Design Automation (CEDA) Chapter.

* Tutorial delivered at ICCD 2015: "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory- NoC Simulation" @ IEEE International Conference on Computer Design (ICCD), 2015, New York City, NY (with Prof. Mark Hempstead, Tufts University, Stephan Diestelhorst, ARM Research).

* Drexel Computer Engineering Graduate Symposium program for Fall, Winter and Spring 2015.
<gallery>
File:symposia-fallFlyer15.png
File:symposia-winterFlyer15.png
File:symposia-springFlyer15.png
</gallery>

* Two familiar faces on the cover of the 2014-15 report from the Drexel Fellowship Office; Paco as a mentor (GRFP 2014) and Scott for having received the NDSEG and GRFP this year in 2015. [http://www.drexel.edu/fellowships/about/overview/Annual%20Report/ Drexel Fellowship Office 2014-2015 Report]

* Mike Lui will give a tutorial on "Communication-Aware Workload Profiling and Memory-NoC Simulation with Sigil and SynchroTrace" @ International Symposium on Workload Characterization (IISWC), 2015.
<gallery>
File:IISWC_flyer.png
</gallery>

* Dr. Taskin and [http://nanocas.ece.stonybrook.edu/salman/ Dr. Salman (Stony Brook University)] gave a tutorial on "Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances" @ IEEE International Symposium on Circuits and Systems (ISCAS), 2015 in Lisbon, Portugal [http://www.iscas2015.org/program/tutorials/].

* Renamed "Drexel VLSI Lab" to "Drexel VLSI and Architecture Lab" to more accurately reflect the current [[Research]] portfolio.

* Scott Lerner received 52nd DAC Richard Newton Young Fellowship from Design Automation Conference in 2015.

* Scott Lerner received the DoD NSDEG fellowship (declined) in 2015.

* Scott Lerner received the NSF GRFP Fellowship in 2015. [http://drexel.edu/fellowships/studentprofiles/profiles/Scott%20Lerner/ Drexel Fellowship Office news]
<gallery>
File:ScottNSF.png
</gallery>

* Giordano Salvador (REU 2013, REU 2014, also independent research, UPenn) received the NSF GRFP Fellowship in 2015, will attend UIUC.

* Michael Miller (REU 2013, Goshen College) received the NSF GRFP Fellowship in 2015, will attend CMU.

* Can Sitik and Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2015.

* Prof. Taskin is the TPC chair for IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2015 [http://sliponline.org]

* Scott Lerner received the A. Richard Newton Young Student Fellow Program travel grant from Design Automation Conference in 2014.

* Karthik Sangaiah received the NSF GRFP Fellowship in 2014. [http://drexel.edu/fellowships/studentprofiles/profiles/Karthik%20Sangaiah/ Drexel Fellowship Office news]
<gallery>
File:PacoNSF.png
</gallery>

* Can Sitik received the Leroy L. Rosser fellowship from Drexel University in 2014.

* Karthik Sangaiah received the George Hill, Jr. fellowship from Drexel University in 2014.

* Best paper nomination for Can Sitik at the ACM GLSVLSI 2013 for the paper entitled [[media:Can_GLSVLSI13.pdf‎|"Skew-Bounded Low Swing Clock Tree Optimization"]].

* Can Sitik received the George Hill, Jr. fellowship from Drexel University in 2013.

* Prof. Taskin is selected the "Young Electrical Engineer of the Year 2013" by the IEEE Philadelphia Section.

* Prof. Taskin organized and presented a tutorial on "Resonant Clocking" with Prof. Matthew Guthaus of UCSC and Drexel VLSI Lab Alumni Dr. Vinayak Honkote of Intel at the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2012 in San Jose, CA. [http://iccad.com/2012_event_details?id=149-10-D program link]

* Drexel student newspaper article on hybrid wireless NoC project [http://thetriangle.org/2012/08/31/antennas-allow-microchips-to-go-wireless/ Drexel Triangle link]
* News release from Drexel about our hybrid wireless NoC project [http://www.drexel.edu/now/news-media/releases/archive/2012/August/Wireless-Network-on-Chip/ August 2012 DrexelNOW link]
<gallery>
File:Chip_CourtesyBarisTaskin-300x225.jpg
File:microchip.jpg
</gallery>

* Dr. Taskin received the ACM SIGDA Distinguished Service Award in 2012.

* Ying Teng received the George Hill, Jr. fellowship from Drexel University in 2012.

* See our article titled [[WirelessInterconnect|"What is Wireless Interconnect?"]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.

* Ying Teng received the N. Bilgutay fellowship from the Department of Electrical & Computer Engineering, Drexel University in 2011.

* Here is the report for the Drexel Office of International Programs travel award for Dr. Taskin to ISCAS'11. [http://www.drexel.edu/international/assets/pdf/ita/faculty/2011-Taskin_Baris.pdf]
<gallery>
File:Facultyspotlight.png
</gallery>

* Ying Teng's first journal paper "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect" is featured on the cover of the Journal of Low Power Electronics (JOLPE) in December 2010. Check out the [[Publications]] page for details.
<gallery>
File:JOLPEDec10.jpg
File:jlp64Fig.png
</gallery>

* Ankit More received the George Hill, Jr. fellowship from Drexel University in 2010.

* Jianchao Lu and Ying Teng presented their work in University Booth, at the ACM/IEEE Design Automation Conference in Anaheim, CA, in 2010.
<gallery>
File:Jianchao_2010_dac.JPG
File:Ying_2010_dac.JPG
</gallery>

* Sharat Chandra recipient of the Young Student Support Program Award for the Design Automation Conference in Anaheim, CA in 2010:
[http://www.sigda.org/youngstudent.html Young Student Support Program DAC]

* The NSF-funded REU Site opportunity on "Computing for Power and Energy" directed by Dr. Taskin is starting in Summer 2010: [http://reu.ece.drexel.edu REU Site on Computing for Power and Energy: The Old, The New and The Renewable]. This site will run for the next three years.
<gallery>
File:DrexelREU2010web.jpg
</gallery>

* Vinayak received the first N. Bilgutay fellowship from the Department of Electrical & Computer Engineering, Drexel University in 2010.

* Jianchao Lu and Vinayak Honkote presented their work in University Booth and Ph.D. Forum, respectively, at the ACM/IEEE Design Automation Conference in San Francisco, CA, in 2009.
<gallery>
File:dac2009_jianchao.jpg
File:dac2009_vinayak.jpg
</gallery>

* Jianchao Lu and Vinayak Honkote participated in the SIGDA CADAthlon at ICCAD 2008 in San Jose, CA.
<gallery>
File:cadathlon080.jpg
File:cadathlon081.jpg
File:cadathlon082.jpg
</gallery>

* Accepting the ''A. Richard Newton Award'' at the ACM/IEEE Design Automation Conference in 2007.
<gallery>
File:dac2007.jpg
File:dac20071.jpg
</gallery>

* Drexel Senior Design team, also winners of the CE award, presented at the University Booth at the ACM/IEEE Design Automation Conference in San Diego, CA, in 2007.
<gallery>
File:senior07.jpg
File:senior071.jpg
File:senior072.jpg
</gallery>

Vasil Pano

2020-10-04T19:58:38Z

Vasil: /* Publications */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Electrical Engineering, 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (March 2020)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, '''Vasil Pano''', and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020. [https://ieeexplore.ieee.org/document/9181128 PAPER]
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Publications

2020-04-17T20:05:04Z

Vasil: /* Thesis and Dissertations */

== Conferences ==
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
#Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Vasil Pano, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A11328 Wireless Network on Chip for Multi-Die Systems]'', 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Vasil Pano

2020-03-02T15:25:07Z

Vasil: /* Resume - Curriculum Vitae */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Electrical Engineering, 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (March 2020)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, '''Vasil Pano''', and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-03-02T15:23:39Z

Vasil: /* Resume - Curriculum Vitae */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Electrical Engineering, 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (February 2020)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, '''Vasil Pano''', and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-02-18T22:42:18Z

Vasil: /* Education */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Electrical Engineering, 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, '''Vasil Pano''', and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-02-17T16:51:28Z

Vasil: /* Conference Publications */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#Ragh Kuttappa, Steven Khoa, Leo Filippini, '''Vasil Pano''', and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

File:Vasil Pano Resume.pdf

2020-02-16T17:54:52Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

Publications

2020-02-13T15:22:49Z

Vasil: /* Journals */

== Conferences ==
#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
#Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Vasil Pano, Ph.D. Dissertation: Wireless Network on Chip for Multi-Die Systems, 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Vasil Pano

2020-02-13T15:22:10Z

Vasil: /* Journal Publications */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-02-13T15:22:00Z

Vasil: /* Journal Publications */

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging
and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf PRE-PRINT]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

File:VasilPano JETCAS Multi-Band.pdf

2020-02-13T15:21:47Z

Vasil:

People

2020-02-10T18:55:10Z

Vasil:

== Faculty ==
[[Baris Taskin]]

[[Baris Taskin | [Biography, Curriculum Vitae and Contact Info]]]



== Ph.D. Students ==

[[Ragh Kuttappa]]

[[Scott Lerner]]

[[Michael Lui]]

[[Karthik Sangaiah]]

[[Dongen Bradley Zhou]]

== MS Students ==



== Undergraduate Researchers ==

Angela Wei (2019) [Drexel]

Steven Khoa (2019) [Drexel]

Albert Emanuel Milani (2019) [Drexel, REU]

Kathrina Waugh (2018) [Drexel STARS scholar]

Rhea Dutta (2018) [Drexel STARS scholar]

Neil Eelman (2018-2019) [Drexel]

Irmak Gezginer (2017) [Middle East Technical University]

Daniel Heuckeroth (2016) [Drexel STARS scholar]

Albert Emanuel Milani (2016) [Drexel STARS scholar]

Nazzareno Farnesi (2016) [Drexel, Drexel STARS scholar]

Brian Hosler (2015-2016) [Drexel]

Eric Leggett, Jr (2015-2016) [Drexel]

Gabrielle Madden (2015) [Drexel STARS scholar]

Isikcan Yilmaz (2015-2016) [Drexel, MS at Drexel]

Eronides Felisberto Da Silva Neto (2015) [Temple]

George Slavin (2015) [Drexel]

Habeeb Olawin (2014) [Drexel STARS scholar]

Fernando Ellis (2013) [RIT - NSF REU]

Daniel Schoepflin (2013) [Drexel STARS scholar]

Giordano Salvador (2013-2014) [Penn - NSF REU, GRFP 2015, PhD at UIUC]

[[Vasil Pano]] (2013-2014) [Drexel, PhD at Drexel]

Andrew Apollonsky (2012) [Cooper Union - NSF REU]

Michael Miller (2012) [Goshen College - NSF REU, GRFP 2015, grad school at CMU]

Michael Sineriz (2012) [Maryland - NSF REU]

[[Scott Lerner ]](2012-2014) [Drexel, GRFP 2015, PhD at Drexel]

Isuru Daulagala (2012) [Drexel]

Catherine Leis (2011) [Drexel, MS at Penn]

Asha Habib (2011) [Bryn Mawr College - NSF REU]

Kevin Linger (2011) [University of Virginia - NSF REU]

Andrew Richard Benton (2011) [Drexel STARS scholar]

David Hocky (2011) [Drexel STARS scholar]

Yusuf Aksehir (2010) [Sabanci University]

Abdalla Musmar (2010) [An-Najah National University - NSF REU, graduate school at CMU]

Michael Edoror (2010) [University of Maryland - NSF REU]

Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]

S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at U of Texas-Austin]

Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]

Danh Nguyen (2007) [Ph.D. at Drexel University]

*Director of REU Site: Computing for Power and Energy (2010-2013) http://reu.ece.drexel.edu

== Senior Design Advisees ==

Scott Szybist, Anthony Romano, Darshan Donthi (2016-2017)

George Slavin, Eric Rock, Avik Bag (2016-2017) (primary advisor Dr. Kandasamy)

David Hong, Isikcan Yilmaz, Stephen Yohannan (2015-2016)

Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano (2013-2014)

Jeffrey Eckert, Neev Wanvari (2012-2013)

Kevin Daly, Tiffany Lakins, Ramen Tieu (2010-2011)

Eric Fargnoli, Colby Weingarten (2009-2010)

Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak (2008-2009)

Andy Chiu, Jonathan Salkind, Daniel Venutolo (2006-2007)

Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner (2006-2007)

James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers (2006-2007)

Jonathan Gevaryahu, Nemanja Milosavljevic, Ana Luiza Silva, Mary Vuong (2006-2007)

David Dimm, Roshani Patel (2005-2006)

== High-School Researchers ==

Ioannis A. Savidis (2019)

Edison Kim (2016)

Ilteris K. Canberk (2010) [Robert College, undergraduate at Carnegie Mellon University]

== Group Alumni ==

=== PhD graduates ===

[[Vasil Pano]] (Ph.D. 2019) [First job: Post Doctoral Researcher], Dissertation: "Wireless Network on Chip for Multi-Die Systems"

[[Leo Filippini]] (Ph.D. 2019) [First job: Voxtel, OR], Dissertation: "Charge Recovery Circuits"

[[Rizwana Begum]] (Ph.D., 2016) [First job: Intel], Dissertation: ''Energy Management of Multi-Component Computing Platforms Under Energy Constraints'' (advisor: Mark Hempstead, Tufts University)

[[Can Sitik]] (Ph.D., 2015) [First job: Intel], Dissertation: ''Design and Automation of Voltage-Scaled Clock Networks''

[[Ying Teng]] (Ph.D., 2014) [First job: Apple], Dissertation: ''Low Power Resonant Rotary Global Clock Distribution Network Design''

[[Ankit More]] (Ph.D., 2013) [First job: Intel], Dissertation: ''Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)''

[[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys, currently at LinkedIn], Dissertation: ''High Performance IC Clock Networks with Grid and Tree Topologies''

[[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel, Bangalore currently at Intel, OR], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''

=== MS graduates ===

Adarsha Balaji (MS, 2018) [Ph.D. at Drexel University]

Isikcan Yilmaz (MS, 2018) [First job: Apple]

Stephen DeLuca (MS, 2015) [First job: Intel]

Julian Kemmerer, (MS 2014) [First job: Susquehanna International Group]

Swetha George (MS 2012) [Ph.D. at the University of Rochester]

Kevin Daly (MS, 2011)

[[Sharat C. Shekar]] (MS, 2011) [First job: Samsung Austin Research, currently at Apple]

Xiaomi Mao (MS, 2011) [First job: Oracle/Sun]

Yaswanth Simhadri (MS, 2008)

Shannon M. Kurtas (BS/MS, 2007) [First job: Intel, currently at Deutsche Bank], Thesis: ''Statistical Static Timing Analysis of Nonzero Clock Skew Circuits''

=== Visiting graduate students ===

Milene Douarche (2017) [MS student visiting from Grenoble Institute of Technology, France]

Jonghoon Oh (2016) [PhD student visiting from Japan Advanced Institute of Technology, Japan]

Sophie Germain (2015) [MS student visiting from Grenoble Institute of Technology, France]

Vasil Pano

2020-01-29T16:52:07Z

Vasil:

[[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-01-29T16:51:58Z

Vasil:

[[File:vasil_pic.jpg|275px|thumb|right|[Vasil Pano]]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-01-29T16:51:50Z

Vasil:

[[File:vasil_pic.jpg|275px|thumb|right|Vasil Pano]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-01-29T16:51:42Z

Vasil:

Vasil Pano

2020-01-29T16:51:26Z

Vasil:

[[File:vasil_pic.jpg|300px|thumb|right|Vasil Pano]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-01-29T16:51:14Z

Vasil:

[[File:vasil_pic.jpg|200px|thumb|right|Vasil Pano]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-01-29T16:51:03Z

Vasil:

[[File:vasil_pic.jpg|175px|thumb|right|Vasil Pano]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-01-29T16:49:09Z

Vasil:

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2020-01-29T16:48:54Z

Vasil:

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]|5px]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

File:Vasil pic.jpg

2020-01-29T16:48:13Z

Vasil: Vasil uploaded a new version of File:Vasil pic.jpg

File:Vasil pic.jpg

2020-01-29T16:47:33Z

Vasil: Vasil uploaded a new version of File:Vasil pic.jpg

Publications

2019-12-22T14:17:19Z

Vasil: /* Journals */

== Conferences ==
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Vasil Pano, Ph.D. Dissertation: Wireless Network on Chip for Multi-Die Systems, 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Publications

2019-12-22T14:17:05Z

Vasil: /* Conferences */

== Conferences ==
#Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Mark Hempstead, and Baris Taskin, "SnackNoc: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020.
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement using Per-Port Router Utilization", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, "A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results", in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication", ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, and Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', Vol. 13, No. 9, pp. 1438--1442, July 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, "The adiabatically driven strongarm comparator", ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', Vol.66, No. 12, pp. 1957--1961, December 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs", ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Vasil Pano, Ph.D. Dissertation: Wireless Network on Chip for Multi-Die Systems, 2019

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Vasil Pano

2019-12-22T14:16:44Z

Vasil: /* Conference Publications */

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]|25px]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2019-12-22T14:16:34Z

Vasil: /* Journal Publications */

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]|25px]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", ''IET Microwaves, Antennas & Propagation (MAP)'', December 2019. [http://vlsi.ece.drexel.edu/images/f/f8/IET_TSVA_finalDraft.pdf DRAFT PAPER]
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao, Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

File:IET TSVA finalDraft.pdf

2019-12-22T14:15:35Z

Vasil:

Vasil Pano

2019-12-11T20:25:06Z

Vasil: /* Resume - Curriculum Vitae */

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]|25px]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (December 2019)]]

== Publications ==
====Journal Publications====
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao, Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

File:Vasil Pano Resume.pdf

2019-12-11T20:24:28Z

Vasil: Vasil uploaded a new version of File:Vasil Pano Resume.pdf

Vasil Pano

2019-11-24T02:49:16Z

Vasil: /* Conference Publications */

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]|25px]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (September 2019)]]

== Publications ==
====Journal Publications====
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao, Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Publications

2019-11-03T14:00:10Z

Vasil:

== Conferences ==
#Vasil Pano, Ragh Kuttappa, and Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#Longfei Wang, Ragh Kuttappa, Baris Taskin, and Selcuk Kose, "Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2019. [https://ieeexplore.ieee.org/document/8771327 PAPER]
#Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Low Voltage Clock Tree Synthesis with Local Gate Clusters", ''Proceedings of the ACM Great Lakes Symposium on Very Large Scale Integration (GLSVLSI)'', May 2019. [https://dl.acm.org/citation.cfm?id=3318004 PAPER]
#Vasil Pano, Ibrahim Tekin, Yuqiao, Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''IEEE International Symposium on Circuits and Systems Late Breaking News (ISCAS-LBN)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#Ragh Kuttappa, Scott Lerner, Leo Filippini, and Baris Taskin, "Low Swing -- Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [https://ieeexplore.ieee.org/document/8702782 PAPER]
#Scott Lerner and Baris Taskin, "Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis", ''Proceedings of the IEEE International Green and Sustainable Computing Conference (IGSC)'', October 2018.
#Oday Bshara, Yuqiao Liu, Ibrahim Tekin, Baris Taskin, and Kapil R. Dandekar, "mmWave Antenna Gain Switching to Mitigate Indoor Blockage", ''Proceedings of the IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS-URSI)'', July 2018. [https://ieeexplore.ieee.org/document/8608384 PAPER]
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, Vasil Pano, and Baris Taskin, “NoC Router Lifetime Improvement using Per-Port Router Utilization,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#Ragh Kuttappa and Baris Taskin, "Low Frequency Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018, pp. 1--5. [https://ieeexplore.ieee.org/document/8351205 PAPER]
#Leo Filippini and Baris Taskin, “A 900 MHz Charge Recovery Comparator with 40 fJ Per Conversion,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351120 PAPER]
#Michael Lui, Karthik Sangaiah, Mark Hempstead, and Baris Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", ''IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)'', April 2018. [https://ieeexplore.ieee.org/document/8366951 PAPER]
#Leo Filippini, Lunal Khuon, and Baris Taskin, "Charge Recovery Implementation of an Analog Comparator: Initial Results," in ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', Aug. 2017, pp. 1505--1508. [https://ieeexplore.ieee.org/document/8053220 PAPER]
#Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 188--193. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#Scott Lerner and Baris Taskin, "WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017, pp. 465--470. [https://ieeexplore.ieee.org/document/7987563 PAPER]
#Leo Filippini and Baris Taskin, "A Charge Recovery Logic System Bus", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974909 PAPER]
#Scott Lerner, Eric Leggett and Baris Taskin, "Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2017. [https://ieeexplore.ieee.org/document/7974910 PAPER]
#Ragh Kuttappa, Leo Filippini, Scott Lerner and Baris Taskin, "Stability of Rotary Traveling Wave Oscillators Under Process Variations and NBTI", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2017, pp. 1--4. [https://ieeexplore.ieee.org/document/8050435 PAPER]
#Ragh Kuttappa, Lunal Khuon, Bahram Nabet and Baris Taskin, "Reconfigurable Threshold Logic Gates using Optoelectronic Capacitors", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2017, pp. 614--617. [https://ieeexplore.ieee.org/document/7927060 PAPER]
#Scott Lerner and Baris Taskin, "Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 379--384. [https://ieeexplore.ieee.org/document/7918345 PAPER]
#Leo Filippini, Diane Lim, Lunal Khuon and Baris Taskin, "Wireless Charge Recovery System for Implanted Electroencephalography Applications in Mice", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2017, pp. 342--345. [https://ieeexplore.ieee.org/document/7918339 PAPER]
#Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 480--486. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016, pp. 400--403. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Leo Filippini and Baris Taskin, "Charge Recovery Logic for Thermal Harvesting Applications", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 542--545. [https://ieeexplore.ieee.org/document/7527297 PAPER]
# Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016, pp. 259--2598. [http://www.ece.stonybrook.edu/~emre/papers/07539124.pdf PAPER]
#Karthik Sangaiah, Mark Hempstead and Baris Taskin, "Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling", ''Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2015, pp. 365--372. [https://ieeexplore.ieee.org/document/7372593 PAPER]
#Leo Filippini, Emre Salman, Baris Taskin, "A Wirelessly Powered System with Charge Recovery Logic", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2015, pp. 505--510. [https://ieeexplore.ieee.org/document/7357158 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", to appear in the ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015. [http://www.ece.sunysb.edu/~emre/papers/TECHCON_2015.pdf PAPER]
#Mallika Rathore, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306. [https://dl.acm.org/citation.cfm?id=2742095 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288. [https://dl.acm.org/citation.cfm?id=2742092 PAPER]
#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Enhanced Level Shifter for Multi-Voltage Operation,” ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp.1442--1445. [https://ieeexplore.ieee.org/document/7168915 PAPER]
#Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015, pp. 1--6. [https://ieeexplore.ieee.org/document/7120367 PAPER]
#[[File:SynchroTrace_new.jpg|link=SynchroTrace|right|120px|border]] Siddharth Nilakantan, Karthik Sangaiah, Ankit More, Giordano Salvador, Baris Taskin, Mark Hempstead, ” SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, ''Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015)'', March 2015, pp. 278--287. [https://ieeexplore.ieee.org/document/7095813 PAPER]
#Giordano Salvador, Siddharth Nilakantan, Baris Taskin, Mark Hempstead and Ankit More, "Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 129--134. [https://ieeexplore.ieee.org/document/7031720 PAPER]
#Siddharth Nilakantan, Scott Lerner, Mark Hempstead and Baris Taskin, "Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation", ''Proceedings of the IEEE/ACM International Conference on VLSI Design (VLSID)'', January 2015, pp. 135--140. [https://ieeexplore.ieee.org/document/7031721 PAPER]
#Ying Teng and Baris Taskin, "Frequency-Centric Resonant Rotary Clock Distribution Network Design", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2014, pp. 742--749. [https://ieeexplore.ieee.org/document/7001434 PAPER]
# Can Sitik, Scott Lerner and Baris Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236. [https://ieeexplore.ieee.org/document/6974686 PAPER]
# Giordano Salvador, Siddharth Nilakantan, Ankit More, Baris Taskin and Mark Hempstead "Static Thread Mapping for NoC CMPs via Binary Instrumentation Traces", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 517--520. [https://ieeexplore.ieee.org/document/6974731 PAPER]
#Can Sitik, Leo Filippini, Emre Salman and Baris Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503. [https://ieeexplore.ieee.org/document/6903413 PAPER]
#Julian Kemmerer and Baris Taskin, "Range-based Dynamic Routing of Hierarchical On Chip Network Traffic", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)", June 2014, pp. 1-9. [https://ieeexplore.ieee.org/document/6886040 PAPER]
#Ying Teng and Baris Taskin, "Resonant Frequency Divider Design Methodology for Dynamic Frequency Scaling", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2013, pp. 479--482. [https://ieeexplore.ieee.org/document/6657087 PAPER]
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31. [https://ieeexplore.ieee.org/document/6566697 PAPER]
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214. [https://dl.acm.org/citation.cfm?doid=2483028.2483094 PAPER]
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54. ''Best Paper Nominee''. [https://dl.acm.org/citation.cfm?id=2483059 PAPER]
# Ying Teng and Baris Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 349--350. [https://dl.acm.org/citation.cfm?id=2483137 PAPER]
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013.
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013, pp. 1229--1234. [https://ieeexplore.ieee.org/document/6513701 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. [https://ieeexplore.ieee.org/document/6386749 PAPER]
# Matthew Guthaus and Baris Taskin, "High-Performance, Low-Power Resonant Clocking: Embedded tutorial", ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 742--745. [https://ieeexplore.ieee.org/document/6386756 PAPER]
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. [https://ieeexplore.ieee.org/document/6378641 PAPER]
# Ying Teng and Baris Taskin, "Clock Mesh Synthesis Method using Earth Mover's Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 121--126. [https://ieeexplore.ieee.org/document/6378627 PAPER]
# Ying Teng and Baris Taskin, "Synchronization Scheme for Brick-Based Rotary Oscillator Arrays", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012, pp. 117--122. [https://dl.acm.org/citation.cfm?id=2206812 PAPER]
# Ankit More and Baris Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2012, pp. 640--643. [https://ieeexplore.ieee.org/document/6272113 PAPER]
# Vinayak Honkote, Ankit More and Baris Taskin, "3-D Parasitic Modeling for Rotary Interconnects", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2012, pp. 137--142. [https://ieeexplore.ieee.org/document/6167742 PAPER]
# Ankit More and Baris Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 19-24. [https://ieeexplore.ieee.org/document/6081370 PAPER]
# Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2011, pp. 273--278. [https://ieeexplore.ieee.org/document/6081408 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 2D Wireless NoC", ''Proceedings of the IEEE International Workshop on System Level Interconnect Prediction (SLIP)'', June 2011. [https://dl.acm.org/citation.cfm?id=2134238 PAPER]
# Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2011, pp. 72--75. [https://ieeexplore.ieee.org/document/5937096 PAPER]
# Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp. 1219--1222. [https://ieeexplore.ieee.org/document/5937789 PAPER]
# Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2011, pp 1940--1943. [https://ieeexplore.ieee.org/document/5937969 PAPER]

# Ying Teng and Baris Taskin, "Process Variation Sensitivity of the Rotary Traveling Wave Oscillator", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011, pp. 236--242. [https://ieeexplore.ieee.org/document/5770731 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011, pp. 131--138. [https://dl.acm.org/citation.cfm?id=1960426 PAPER]
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011, pp. 455--460. [https://ieeexplore.ieee.org/document/5763079 PAPER]

# Vinayak Honkote and Baris Taskin, "Skew-Aware Capacitive Load Balancing for Low-Power Zero Clock Skew Rotary Oscillatory Array", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2010, pp. 209--214. [https://ieeexplore.ieee.org/document/5647781 PAPER]
# Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", ''Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)'', September 2010, pp. 105--108. [https://ieeexplore.ieee.org/document/5616198 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of On-chip Antennas for a Reconfigurable Hybrid 3D Wireless NoC", ''Proceedings of the IEEE International SoC Conference (SOCC)'', September 2010, pp. 447--452. [https://ieeexplore.ieee.org/document/5784673 PAPER]
# Ankit More and Baris Taskin, "Effect of EMI between Wireless Interconnects and Metal Interconnects on CMOS Digital Circuits", ''Proceedings of the Mediterranean Microwave Symposium (MMS)'', August 2010. [http://vlsi.ece.drexel.edu/images/3/38/MMS_2010_Ankit.pdf PAPER]
# Vinayak Honkote and Baris Taskin, "PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', August 2010, pp. 111--116. [https://ieeexplore.ieee.org/document/5599002 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", ''Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation'', July 2010, pp. 1--4. [https://ieeexplore.ieee.org/abstract/document/5562072 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 228-231. [https://ieeexplore.ieee.org/document/5572776 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp.17-22. [https://ieeexplore.ieee.org/document/5572752 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation and Analysis of Resonant Rotary Clocking Technology", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010, pp. 471--472. [https://ieeexplore.ieee.org/document/5572817 PAPER]
# Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", ''Proceedings of the System Level Interconnect Prediction (SLIP)'', June 2010, pp. 35--41. [https://dl.acm.org/citation.cfm?id=1811111 PAPER]
# Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", ''Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)'', May 2010, pp. 413-416. [https://dl.acm.org/citation.cfm?doid=1785481.1785577 PAPER]
# Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 49--53. [https://ieeexplore.ieee.org/document/5450405 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770. [https://ieeexplore.ieee.org/document/5450493 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 413--417. [https://ieeexplore.ieee.org/document/5450544 PAPER]
# Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array", ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2010, pp. 218--223. [https://ieeexplore.ieee.org/document/5401322 PAPER]
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 232--236. [https://ieeexplore.ieee.org/document/5423805 PAPER]
# Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp. 165--168. [https://ieeexplore.ieee.org/document/5423896 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227. [https://ieeexplore.ieee.org/document/5236113 PAPER]
# Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",'' Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 1147--1150. [https://ieeexplore.ieee.org/document/5235937 PAPER]
# Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 232--235. [https://ieeexplore.ieee.org/document/5236111 PAPER]
# Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2009, pp. 588--593. [https://ieeexplore.ieee.org/document/4810360 PAPER]
# Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2008, pp. 114--119. [https://ieeexplore.ieee.org/document/4751849 PAPER]
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84. [https://ieeexplore.ieee.org/document/4616741 PAPER]
# Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 605--608 ''Best student paper award nominee''. [https://ieeexplore.ieee.org/document/4616872 PAPER]
# Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 442--445. [https://ieeexplore.ieee.org/document/4616831 PAPER]
# Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)'', October 2007, pp. 54--61. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education", ''Proceedings of the International Conference on Microelectronic Systems Education (MSE)'', June 2007, pp. 65--66. [https://ieeexplore.ieee.org/document/4231452 PAPER]
#Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 486--490. [https://ieeexplore.ieee.org/document/4267397 PAPER]
# Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking", ''Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)'', August 2006, pp. 261--265. [https://ieeexplore.ieee.org/document/4267124 PAPER]
# Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design", ''Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)'', July 2006, pp. 302--305. [https://ieeexplore.ieee.org/document/1717085 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', Apr. 2005, pp. 47--54. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 607--610. [https://ieeexplore.ieee.org/document/1399754 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits", ''Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)'', December 2004, pp. 603--606. [https://ieeexplore.ieee.org/document/1399753 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2004, Vol. 2, pp. II-617--620. [https://ieeexplore.ieee.org/document/1329347 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew", ''Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)'', December 2002, pp. 111--117. [https://dl.acm.org/citation.cfm?doid=589411.589437 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches", ''Proceedings of the IEEE International ASIC/SOC Conference'', September 2002, pp. 358--362. [https://ieeexplore.ieee.org/document/1158085 PAPER]

== Journals ==
# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Accepted July 2019. [https://ieeexplore.ieee.org/document/8815869 PAPER]
# Yuqiao Liu, Oday Bshara, Ibrahim Tekin, Christopher Israel, Ahmad Hoorfar, Baris Taskin, Kapil Dandekar, "Design and Fabrication of a Two-Port Three-Beam Switched Beam Antenna Array for 60 GHz Communication", ''IET Microwaves, Antennas & Propagation'', March 2019. [https://digital-library.theiet.org/content/journals/10.1049/iet-map.2018.6010 PAPER]
# Leo Filippini and Baris Taskin, “The adiabatically driven strongarm comparator,” ''IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)'', February 2019. [https://ieeexplore.ieee.org/document/8630648 PAPER]
# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
# Weicheng Liu, Can Sitik, Savithri Sundareswaran, Benjamin Huang, Emre Salman and Baris Taskin, "SLECTS: Slew-Driven Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No.4, pp.864--874, April 2019. [https://ieeexplore.ieee.org/document/8607103 PAPER]
#Scott Lerner, Isikcan Yilmaz, and Baris Taskin, "Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', vol. 27, No. 3, pp. 700-710, March 2019. [https://ieeexplore.ieee.org/document/8536898 PAPER]
#Scott Lerner and Baris Taskin, "Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 27, No. 1, pp. 1-10, January 2019. [https://ieeexplore.ieee.org/document/8510827 PAPER]
#Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 37, No. 9, pp. 1853--1866, September 2018. [https://ieeexplore.ieee.org/document/8090893 PAPER]
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ''ACM Transactions on Architecture and Code Optimization (TACO)'', Vol. 15, No. 1, Article 2, March 2018. [https://dl.acm.org/citation.cfm?id=3158642 PAPER]
# Can Sitik, Weicheng Liu, Baris Taskin and Emre Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks," ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 24, No. 10, pp. 3080--3093, October 2016. [https://ieeexplore.ieee.org/document/7442134 PAPER]
# Ankit More and Baris Taskin, "Locality-Aware Network Utilization Balancing in NoCs", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 21, No. 1, Article 6, November 2015. [https://dl.acm.org/citation.cfm?id=2743012 PAPER]
# Ying Teng and Baris Taskin, "ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 23, No. 11, pp. 2519--2530, November 2015. [https://ieeexplore.ieee.org/document/7097055 PAPER]
# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015. [https://dl.acm.org/citation.cfm?id=2701617 PAPER]
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014. [https://www.sciencedirect.com/science/article/pii/S0167926013000564 PAPER]
# Vinayak Honkote and Baris Taskin, "ZeROA: Zero Clock Skew Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 8, pp. 1528--1532, August 2012. [https://ieeexplore.ieee.org/document/5936660 PAPER]
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 20, No. 6, pp. 1002--1011, June 2012. [https://ieeexplore.ieee.org/document/5782973 PAPER]
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 31, No. 2, pp. 217--227, February 2012. [https://ieeexplore.ieee.org/document/6132652 PAPER]
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 16, No. 4, Article 49, October 2011. [https://dl.acm.org/citation.cfm?doid=2003695.2003709 PAPER]
# Vinayak Honkote and Baris Taskin, "CROA: Design and Analysis of Custom Rotary Oscillatory Array", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 19, No. 10, pp. 1837--1847, October 2011. [https://ieeexplore.ieee.org/document/5556059 PAPER]
# Shannon M. Kurtas and Baris Taskin, "Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling", ''International Journal of Circuits, Systems and Computers (JCSC)'', Vol. 20, No. 5, pp. 881--898, 2011. [https://www.worldscientific.com/doi/abs/10.1142/S0218126611007669 PAPER]
# Kyle Yencha, Matthew Zofchak, Daniel Oakum, Gerre Strait, Baris Taskin, Bahram Nabet, "Design of an Addressable Internetworked Microscale Sensor", ''Special Issue: Journal of Selected Areas in Microelectronics (JSAM)'', December 2010, ISSN: 1925-2676. [http://www.cyberjournals.com/Papers/Dec2010/03.pdf PAPER]
# [[File:JOLPEDec10_small.jpg|right|border|frame|15px]] Ying Teng and Baris Taskin, "Look-up Table Based Low Power Rotary Traveling Wave Design Considering the Skin Effect", ''Journal of Low Power Electronics (JOLPE)'', Vol. 6, No. 4, pp. 491--502, December 2010, '''Cover feature'''. [https://www.ingentaconnect.com/contentone/asp/jolpe/2010/00000006/00000004/art00003%3bjsessionid=2als4gigrt6n.x-ic-live-02 PAPER]
# Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", ''Journal of VLSI Design'', Volume 2010 (2010), Article ID 451809. [https://www.hindawi.com/journals/vlsi/2010/451809/ PAPER]
# Baris Taskin and Ivan S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit", ''International Journal on Circuits, Systems and Computers (JCSC)'', Vol. 18, No. 5, pp. 899--908, July 2009. [https://www.worldscientific.com/doi/abs/10.1142/S0218126609005423 PAPER]
# Baris Taskin, Joseph DeMaio, Owen Farell, Michael Hazeltine, Ryan Ketner, "Custom Topology Rotary Clock Router", ''ACM Transactions on Design Automation of Electronic Systems (TODAES)'', Vol. 14, No. 3, Article 44, May 2009. [https://dl.acm.org/citation.cfm?id=1529266 PAPER]
# Baris Taskin, Andy Chiu, Joseph Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture", ''ACM Journal on Emerging Technologies and Computation (JETC)'', Vol. 5, No. 1, Article 4, January 2009. [https://ieeexplore.ieee.org/document/4400858 PAPER]
# Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 16, No. 12, pp. 1648--1656, December 2008. [https://ieeexplore.ieee.org/document/4624551 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling", ''IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)'', Vol. 25, No. 4, pp. 651--663, April 2006. [https://ieeexplore.ieee.org/document/1610731 PAPER]
# Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Vol. 12, No. 1, pp. 12--27, January 2004. [https://ieeexplore.ieee.org/document/1263555 PAPER]

== Books and Book Chapters ==

# Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, ''Timing Optimization through Clock Skew Scheduling'', Springer, 2009, ISBN-13: 978-0387710556.
# Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, ''System Timing'', Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

<gallery>
File:springerbookcover.jpg|Springer link [http://www.springer.com/engineering/circuits+&+systems/book/978-0-387-71055-6]
File:handbookcover.jpg|Amazon link [http://www.amazon.com/VLSI-Handbook-Second-Electrical-Engineering/dp/084934199X/ref=dp_ob_title_bk]
</gallery>



== Thesis and Dissertations ==

* Leo Filippini, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A9440 Charge Recovery Circuits]'', 2019

* A. Can Sitik, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A7277 Design and Automation of Voltage-Scaled Clock Networks]'', 2015

* Ying Teng, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4573 Low Power Resonant Rotary Global Clock Distribution Network Design]'', 2014

* Ankit More, Ph.D. Dissertation: ''[https://idea.library.drexel.edu/islandora/object/idea%3A4196 Network-on-Chip (NoC) Architectures for Exa-Scale Chip-Multi-Processors (CMPs)]'', 2013

* Jianchao Lu, Ph.D. Dissertation, ''[https://idea.library.drexel.edu/islandora/object/idea%3A3526 High Performance IC Clock Networks with Mesh and Tree Topologies]'', 2011

* Vinayak Honkote, Ph.D. Dissertation, ''Design Automation and Analysis of Resonant Clocking Technologies'', 2010

* Shannon M. Kurtas, M.S. Thesis, ''[https://idea.library.drexel.edu/islandora/object/idea%3A1771 Statistical Static Timing Analysis of Nonzero Clock Skew Circuits]'', 2007

Vasil Pano

2019-11-03T13:59:31Z

Vasil: /* Conference Publications */

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]|25px]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (September 2019)]]

== Publications ==
====Journal Publications====
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', Ocotober 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER]
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao, Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]

Vasil Pano

2019-09-19T01:47:36Z

Vasil: /* Resume - Curriculum Vitae */

[[File:vasil_pic.jpg|right|border|frame|[[Vasil Pano]]|25px]]

== Education ==
:'''PhD in Computer Engineering, 2014 - 2019''' 
::Drexel University, Philadelphia, PA.
:'''B.S. in Computer Engineering, 2014''' 
::Drexel University, Philadelphia, PA.

== Research Interests ==
:* Network on Chip
:* Computer Architecture
:* Memory Coherence Protocols
:* Communication Infrastructure

==Resume - Curriculum Vitae==
:[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (September 2019)]]

== Publications ==
====Journal Publications====
#Ragh Kuttappa, Adarsha Balaji, '''Vasil Pano''', Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', January 2019. [https://ieeexplore.ieee.org/document/8653860 PAPER]
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER]

====Conference Publications====
#'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', Ocotober 2019.
#Ragh Kuttappa, Baris Taskin, Scott Lerner, '''Vasil Pano''', and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", ''Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)'', July 2019. [https://ieeexplore.ieee.org/document/8824957 PAPER]
#'''Vasil Pano''', Ibrahim Tekin, Yuqiao, Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2019. [http://vlsi.ece.drexel.edu/images/8/84/ISCAS2019_LateBreakingNews.pdf PAPER]
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER]
#Scott Lerner, '''Vasil Pano''', and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351022 PAPER]
#'''Vasil Pano''', Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2017. [https://ieeexplore.ieee.org/document/7987517 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER]
#'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER]
#Yuqiao Liu, '''Vasil Pano''', Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," ''Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON)'', April 2015. [https://ieeexplore.ieee.org/document/7120367 PAPER]

== Tutorial/Poster Presentations ==
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award'''
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015.
# Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at ''Mid-Atlantic (ASEE)'', 2014

== Teaching Assistant Coursework ==
:; Academic Year 2018-2019
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'')
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'')

:; Academic Year 2017-2018
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'')
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'')
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'')

:; Academic Year 2016-2017
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'')
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'')
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'')

:; Academic Year 2015-2016
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'')
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'')
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'')
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'')
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'')

:; Academic Year 2014-2015
:: Systems Programming (Summer 2014-15, ''Junior Level Class'')
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'')
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'')
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'')

:; Academic Year 2013-2014
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'')
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'')

==Contact Information==
'''Address:''' 
3141 Chestnut Street 
ECE Department, Bossone 405 
Drexel University 
Philadelphia 
Pennsylvania 19104 

'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] 

'''Linkedin:''' [https://www.linkedin.com/in/panovasil Vasil Pano]