Can Sitik - Revision history

Can at 07:11, 7 March 2016

2016-03-07T07:11:19Z

← Older revision		Revision as of 03:11, 7 March 2016
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	==Contact Information==		==Contact Information==
	'''Address:''' <br>		'''Address:''' <br>
	~~3141 Chestnut Street <br>~~		Hillsboro, OR 97124 <br>
	~~Department of ECE <br>~~
	~~Drexel University <br>~~
	~~Bossone 324 <br>~~
	~~Philadelphia~~, ~~PA 19104~~ <br>

	'''Email:''' [mailto:~~as3577~~@~~drexel~~.~~edu as3577~~@~~drexel~~.~~edu~~] <br>		'''Email:''' [mailto:cansitik@gmail.com cansitik@gmail.com] <br>

	'''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&trk=hb_tab_pro_top A. Can Sitik]		'''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&trk=hb_tab_pro_top A. Can Sitik]

Can at 02:28, 29 February 2016

2016-02-29T02:28:35Z

← Older revision		Revision as of 22:28, 28 February 2016
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	====Journals====		====Journals====
	# C. Sitik, W. Liu, B. Taskin and E. Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", (accepted to) ''IEEE Transactions on Very Large Scale Integration ~~(VLSI)~~ Systems (TVLSI)'', January 2016.		# C. Sitik, W. Liu, B. Taskin and E. Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", (accepted to) ''IEEE Transactions on Very Large Scale Integration Systems (TVLSI)'', January 2016.
	# C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.		# C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
	# C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.		# C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.

Can at 02:28, 29 February 2016

2016-02-29T02:28:13Z

← Older revision		Revision as of 22:28, 28 February 2016
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	====Journals====		====Journals====
			# C. Sitik, W. Liu, B. Taskin and E. Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", (accepted to) ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', January 2016.
	# C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.		# C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
	# C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.		# C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.

Can at 02:26, 29 February 2016

2016-02-29T02:26:32Z

← Older revision		Revision as of 22:26, 28 February 2016
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	====Conferences====		====Conferences====
			# W. Liu, E. Salman, C. Sitik and B. Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", to appear in ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.
	#W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.		#W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
	#M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.		#M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.

Taskin: /* Education */

2015-12-19T03:20:35Z

Education

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	==Education==		==Education==
	'''Ph.D. in Computer Engineering, 2011 - ~~Present~~''' <br>		'''Ph.D. in Computer Engineering, 2011 - 2015''' <br>
	:Drexel University, Philadelphia, Pennsylvania, USA		:Drexel University, Philadelphia, Pennsylvania, USA

Can at 22:21, 18 November 2015

2015-11-18T22:21:37Z

Can at 02:55, 17 November 2015

2015-11-17T02:55:48Z

← Older revision		Revision as of 22:55, 16 November 2015
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	====Conferences====		====Conferences====
	#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ~~to appear in the~~ ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.		#Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin, Savithri Sundareswaran and Benjamin Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
	#Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.		#Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.
	#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.		#Weicheng Liu, Emre Salman, Can Sitik and Baris Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.

Can at 20:07, 16 November 2015

2015-11-16T20:07:15Z

← Older revision		Revision as of 16:07, 16 November 2015
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	====Journals====		====Journals====
	# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, ~~pp.~~ 13~~:1--13:20~~, ~~September~~ 2015.		# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
	# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.		# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.

Can at 20:03, 16 November 2015

2015-11-16T20:03:39Z

← Older revision		Revision as of 16:03, 16 November 2015
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	====Journals====		====Journals====
	# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ~~(accepted to)~~ ''ACM Journal of Emerging Technologies in Computing Systems (JETC)''.		# Can Sitik, Emre Salman, Leo Filippini, Sung Jun Yoon and Baris Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, pp. 13:1--13:20, September 2015.
	# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.		# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.

Can at 05:11, 2 September 2015

2015-09-02T05:11:24Z

← Older revision		Revision as of 01:11, 2 September 2015
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	==Research Interests==		==Research Interests==
	* Low Swing Clock Tree Synthesis		* Low Swing Clock Tree Synthesis
			* Pre- and Post-Si Power and Timing Modeling
	* Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]		* Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]
	* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]		* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]
	* Clock Network Design with FinFETs		* Clock Network Design with FinFETs
	* Pre- and Post-Si Power and Timing Modeling

	==Curriculum Vitae==		==Curriculum Vitae==

← Older revision		Revision as of 18:21, 18 November 2015
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	====Journals====		====Journals====
	# ~~Can~~ Sitik, ~~Emre~~ Salman, ~~Leo~~ Filippini, ~~Sung Jun~~ Yoon and ~~Baris~~ Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.		# C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
	# ~~Can~~ Sitik and ~~Baris~~ Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.		# C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.

	====Conferences====		====Conferences====
	#~~Weicheng~~ Liu, ~~Emre~~ Salman, ~~Can~~ Sitik, ~~Baris~~ Taskin, ~~Savithri~~ Sundareswaran and ~~Benjamin~~ Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.		#W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
	#~~Mallika~~ Rathore, ~~Weicheng~~ Liu, ~~Emre~~ Salman, ~~Can~~ Sitik and ~~Baris~~ Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.		#M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.
	#~~Weicheng~~ Liu, ~~Emre~~ Salman, ~~Can~~ Sitik and ~~Baris~~ Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.		#W. Liu, E. Salman, C. Sitik and B. Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.
	#~~Weicheng~~ Liu, ~~Emre~~ Salman, ~~Can~~ Sitik and ~~Baris~~ Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.		#W. Liu, E. Salman, C. Sitik and B. Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.
	# ~~Can~~ Sitik, ~~Scott~~ Lerner and ~~Baris~~ Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.		# C. Sitik, S. Lerner and B. Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.
	# ~~Can~~ Sitik, ~~Leo~~ Filippini, ~~Emre~~ Salman and ~~Baris~~ Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.		# C. Sitik, L. Filippini, E. Salman and B. Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.
	# ~~Can~~ Sitik, ~~Prawat~~ Nagvajara and ~~Baris~~ Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.		# C. Sitik, P. Nagvajara and B. Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.
	# ~~Can~~ Sitik and ~~Baris~~ Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.		# C. Sitik and B. Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.
	# ~~Can~~ Sitik and ~~Baris~~ Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.		# C. Sitik and B. Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.
	# ~~Can~~ Sitik and ~~Baris~~ Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.		# C. Sitik and B. Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.
	# ~~Can~~ Sitik and ~~Baris~~ Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.		# C. Sitik and B. Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.
	[http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&hl=en '''Google Scholar Page''']		[http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&hl=en '''Google Scholar Page''']