Main Page - Revision history

Taskin at 18:12, 5 September 2025

2025-09-05T18:12:16Z

← Older revision		Revision as of 14:12, 5 September 2025
Line 27:		Line 27:
	# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.		# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.
	# ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).		# ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).
	#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage.		<!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage.-->
	<!--# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.-->		<!--# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.-->

Line 72:		Line 72:

	[[Yilmaz Gonul]]		[[Yilmaz Gonul]]

	~~[[Ceyhun Kayan]]~~

	[[Nicholas Sica]]		[[Nicholas Sica]]

Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */

2025-09-05T18:11:38Z

Drexel VLSI and Algorithms Laboratory (VANDAL)

← Older revision		Revision as of 14:11, 5 September 2025
Line 27:		Line 27:
	# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.		# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.
	# ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).		# ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).
	~~<!--~~#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. -->		#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage.
	# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.		<!--# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.-->

Taskin at 19:47, 5 February 2025

2025-02-05T19:47:35Z

← Older revision		Revision as of 15:47, 5 February 2025
Line 70:		Line 70:
	=== Ph.D. students ===		=== Ph.D. students ===

	~~[[Sief Atari]]~~

	[[Yilmaz Gonul]]		[[Yilmaz Gonul]]

	[[Ceyhun Kayan]]		[[Ceyhun Kayan]]

	~~[[Scott Lerner]]~~

	~~[[Michael Lui]]~~

	[[Nicholas Sica]]		[[Nicholas Sica]]

Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */

2025-02-05T15:03:24Z

Drexel VLSI and Algorithms Laboratory (VANDAL)

← Older revision		Revision as of 11:03, 5 February 2025
Line 22:		Line 22:
	# ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.		# ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
	# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.		# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
	#''Unconventional ~~computing~~'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.		#''Unconventional Computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.
	# ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.		# ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.
	# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.		# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.

Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */

2025-02-05T15:02:58Z

Drexel VLSI and Algorithms Laboratory (VANDAL)

← Older revision		Revision as of 11:02, 5 February 2025
Line 23:		Line 23:
	# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.		# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
	#''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.		#''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.
	# "Perturbation Biology Modeling", using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.		# ''Perturbation Biology Modeling'', using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.

	# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.		# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
	# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.		# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.

Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */

2025-02-05T15:02:40Z

Drexel VLSI and Algorithms Laboratory (VANDAL)

← Older revision		Revision as of 11:02, 5 February 2025
Line 23:		Line 23:
	# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.		# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
	#''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.		#''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.
			# "Perturbation Biology Modeling", using algorithmic approaches to assist in the computational processes that identify and predict through machine learning external sources that lead to perturbation in biological systems, a process that is impactful in health sciences and discovery.

	# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.		# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
	# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.		# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.

Taskin: /* Drexel VLSI and Algorithms Laboratory (VANDAL) */

2025-02-05T15:00:20Z

Drexel VLSI and Algorithms Laboratory (VANDAL)

← Older revision		Revision as of 11:00, 5 February 2025
Line 22:		Line 22:
	# ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.		# ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
	# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.		# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
	# "Unconventional computing" using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.		#''Unconventional computing'' using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.
	# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.		# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
	# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.		# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.

Taskin: /* Drexel VLSI and Architecture Laboratory (VANDAL) */

2025-02-05T14:59:44Z

Drexel VLSI and Architecture Laboratory (VANDAL)

← Older revision		Revision as of 10:59, 5 February 2025
Line 4:		Line 4:
	[[File:VANDAL.png\|right\|super\|200px]]		[[File:VANDAL.png\|right\|super\|200px]]

	== Drexel VLSI and ~~Architecture~~ Laboratory (VANDAL) ==		== Drexel VLSI and Algorithms Laboratory (VANDAL) ==

	Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. <!--Grand research goals are:		Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems. <!--Grand research goals are:
Line 17:		Line 17:


	VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning~~, and Cryptocurrencies~~. Some of the most exciting projects currently ongoing involve:		VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures, algorithms and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning. Some of the most exciting projects currently ongoing involve:


			# ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
			# ''Communication Infrastructure for Chip-Multi-Processors'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
			# "Unconventional computing" using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.
	# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.		# ''Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting'': Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
	# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.		# ''Aging-Resilient IoT Hardware'': The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.
	# ''Energy-Efficient Clock Synchronization for Computing Systems'': The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
	# ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).		# ''Hardware and Software Co-Design for Exascale Computing Systems'': With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).
	# ''Communication Infrastructure for Chip-Multi-Processors and 5G IoT systems within Smart Office Spaces'': Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
	<!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. -->		<!--#''Energy-Efficient Clock Synchronization'': Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage. -->
	# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.		# ''Cyber Physical Design Automation of Smart Homes/Smart Cities'': Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.

Njs82: /* Ph.D. students */

2023-02-07T17:38:25Z

Ph.D. students

← Older revision		Revision as of 13:38, 7 February 2023
Line 66:		Line 66:

	=== Ph.D. students ===		=== Ph.D. students ===

			[[Sief Atari]]

			[[Yilmaz Gonul]]

			[[Ceyhun Kayan]]

	[[Scott Lerner]]		[[Scott Lerner]]
Line 72:		Line 78:

	[[Nicholas Sica]]		[[Nicholas Sica]]

	~~[[Sief Atari]]~~

	~~[[Yilmaz Gonul]]~~

	~~[[Ceyhun Kayan]]~~

	=== Other researchers ===		=== Other researchers ===

Njs82: /* Ph.D. students */

2023-02-07T17:25:23Z

Ph.D. students

← Older revision		Revision as of 13:25, 7 February 2023
Line 67:		Line 67:
	=== Ph.D. students ===		=== Ph.D. students ===

	~~Sief Atari~~		[[Scott Lerner]]

	~~Yilmaz Gonul~~		[[Michael Lui]]

	~~Ceyhun Kayan~~		[[Nicholas Sica]]

	[[~~Scott Lerner~~]]		[[Sief Atari]]

	[[~~Michael Lui~~]]		[[Yilmaz Gonul]]

	[[~~Nicholas Sica~~]]		[[Ceyhun Kayan]]

	=== Other researchers ===		=== Other researchers ===