Ragh Kuttappa - Revision history

Ragh: /* Education */

2022-01-21T00:43:28Z

Education

← Older revision		Revision as of 20:43, 20 January 2022
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	==Education==		==Education==
	'''Ph.D. in Electrical Engineering~~, 2021~~''' <br>		'''Ph.D. in Electrical Engineering''' <br>
	:Drexel University, Philadelphia, PA, USA		:Drexel University, Philadelphia, PA, USA

	'''M.S. in Electrical Engineering~~, 2015~~''' <br>		'''M.S. in Electrical Engineering''' <br>
	:San Francisco State University		:San Francisco State University

	'''Bachelor of Engineering~~, 2012~~''' <br>		'''Bachelor of Engineering''' <br>
	:Visvesvaraya Technological University (VTU), Karnataka, India		:Visvesvaraya Technological University (VTU), Karnataka, India

Ragh: /* Résumé */

2022-01-21T00:42:46Z

Résumé

← Older revision		Revision as of 20:42, 20 January 2022
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	<li style="display: inline-block;"> [[File:fastdvfs.png\|thumb\|right\|350px\|Fast DVFS performance improvements and power savings]] </li>		<li style="display: inline-block;"> [[File:fastdvfs.png\|thumb\|right\|350px\|Fast DVFS performance improvements and power savings]] </li>
	</ul></div>		</ul></div>

	~~==Résumé==~~
	~~[[media:Ragh_kuttappa_resume.pdf \| Ragh Kuttappa (February 2021)]]~~

	==Publications==		==Publications==

Ragh: /* Education */

2022-01-19T19:45:21Z

Education

← Older revision		Revision as of 15:45, 19 January 2022
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	==Education==		==Education==
	'''Ph.D. in Electrical Engineering, ~~ongoing~~''' <br>		'''Ph.D. in Electrical Engineering, 2021''' <br>
	:Drexel University, Philadelphia, PA, USA		:Drexel University, Philadelphia, PA, USA

Ragh at 19:44, 19 January 2022

2022-01-19T19:44:59Z

← Older revision		Revision as of 15:44, 19 January 2022
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	~~[[File:Ragh.png\|175px\|thumb\|right\|Ragh Kuttappa]]~~

	==Education==		==Education==

Ragh: /* Journals */

2021-09-03T13:48:49Z

Journals

← Older revision		Revision as of 09:48, 3 September 2021
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	====Journals====		====Journals====
			# Ragh Kuttappa, Longfei Wang, Selcuk Kose, and Baris Taskin, "Multiphase Digital Low-Dropout Regulators", ''IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)'', Accepted September 2021.
	# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636-1645, April 2021.		# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636-1645, April 2021.
	# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.		# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.

Ragh: /* Conferences */

2021-07-16T14:22:59Z

Conferences

← Older revision		Revision as of 10:22, 16 July 2021
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	====Conferences====		====Conferences====
			# Ragh Kuttappa, Leo Fiippini, Nicholas Sica, Baris Taskin, "Scalable Resonant Power Clock Generation for Adiabatic Logic Design", ''Proceedings of the IEEE International Symposium on VLSI (ISVLSI)'', July 2021.
	#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.		#Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.
	#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.		#Ragh Kuttappa and Baris Taskin, "FinFET -- Based Low Swing Rotary Traveling Wave Oscillators", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2020.

Ragh: /* Journals */

2021-03-06T16:10:29Z

Journals

← Older revision		Revision as of 12:10, 6 March 2021
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	====Journals====		====Journals====
	# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', ~~Accepted February~~ 2021.		# Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 68, No. 4, pp. 1636-1645, April 2021.
	# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.		# Ragh Kuttappa, Selcuk Kose, and Baris Taskin, "FOPAC: Flexible On-Chip Power and Clock", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 12, pp. 4628--4636, December 2019.
	# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019.		# Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer", ''IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)'', Vol. 66, No. 7, pp. 2685--2698, July 2019.

Ragh: /* Research Interests */

2021-02-23T15:47:06Z

Research Interests

← Older revision		Revision as of 11:47, 23 February 2021
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	''2. Clock Synchronization for Multi-Die Systems''		''2. Clock Synchronization for Multi-Die Systems''

	Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. The underlying theme for the work ~~in this project~~ is to synchronize chiplets that are in the “same clock domain”, regardless of homogeneous v.s. heterogeneous integration. Initial work and results of this work was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19]. An extension of the [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19] work with a complete methodology is published in [https://ieeexplore.ieee.org/document/9360308 TCAS-I].		Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. The underlying theme for the work is to synchronize chiplets that are in the “same clock domain”, regardless of homogeneous v.s. heterogeneous integration. Initial work and results of this work was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19]. An extension of the [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19] work with a complete methodology is published in [https://ieeexplore.ieee.org/document/9360308 TCAS-I].

Ragh: /* Research Interests */

2021-02-23T15:46:08Z

Research Interests

← Older revision		Revision as of 11:46, 23 February 2021
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	<li style="display: inline-block;"> [[File:RotaSYN_Flow_ragh1.png\|thumb\|left\|500px\|RotaSYN Flow]] </li>		<li style="display: inline-block;"> [[File:RotaSYN_Flow_ragh1.png\|thumb\|left\|500px\|RotaSYN Flow]] </li>

	<li style="display: inline-block;"> [[File:aes_core.png\|thumb\|right\|~~300px~~\|AES core synthesized with RotaSYN]] </li>		<li style="display: inline-block;"> [[File:aes_core.png\|thumb\|right\|350px\|AES core synthesized with RotaSYN]] </li>
	</ul></div>		</ul></div>

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	<div><ul>		<div><ul>
	<li style="display: inline-block;"> [[File:Rotary_interposer_topology.png\|thumb\|left\|~~250px~~\|Active silicon interposer based synchronization topology for multi-die systems with resonant rotary clocks]] </li>		<li style="display: inline-block;"> [[File:Rotary_interposer_topology.png\|thumb\|left\|245px\|Active silicon interposer based synchronization topology for multi-die systems with resonant rotary clocks]] </li>
			<li style="display: inline-block;"> [[File:MDS_flow.png\|thumb\|right\|760px\|Overall synchronization methodology for MDS]] </li>
	<li style="display: inline-block;"> [[File:Rotary_interposer_die.png\|thumb\|right\|~~300px~~\|Multi-die system implemented with CORTEX M0 cores and resonant rotary clocks]] </li>		<li style="display: inline-block;"> [[File:Rotary_interposer_die.png\|thumb\|right\|360px\|Multi-die system implemented with CORTEX M0 cores and resonant rotary clocks]] </li>
	</ul></div>		</ul></div>

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	<li style="display: inline-block;"> [[File:Fopac.png\|thumb\|left\|300px\|FOPAC Architecture]] </li>		<li style="display: inline-block;"> [[File:Fopac.png\|thumb\|left\|300px\|FOPAC Architecture]] </li>

	<li style="display: inline-block;"> [[File:fastdvfs.png\|thumb\|right\|~~300px~~\|Fast DVFS performance improvements and power savings]] </li>		<li style="display: inline-block;"> [[File:fastdvfs.png\|thumb\|right\|350px\|Fast DVFS performance improvements and power savings]] </li>
	</ul></div>		</ul></div>

Ragh: /* Research Interests */

2021-02-23T15:41:04Z

Research Interests

← Older revision		Revision as of 11:41, 23 February 2021
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	</ul></div>		</ul></div>

	''2. ~~Robust Low Power~~ Clock Synchronization for Multi-Die Systems''		''2. Clock Synchronization for Multi-Die Systems''

	Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. ~~This paper~~ was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19].		Multi-Die Systems (MDS) have leveraged the high interconnect performance on active and passive interposers to design Network-on-Chips (NoC). However, synchronizing the MDS with a single clocking domain has never been explored. We design a single clocking domain over the active interposer leveraging the high quality interconnect performance, specifically targeting cross-die synchronization. The underlying theme for the work in this project is to synchronize chiplets that are in the “same clock domain”, regardless of homogeneous v.s. heterogeneous integration. Initial work and results of this work was presented at [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19]. An extension of the [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8824957 ISLPED'19] work with a complete methodology is published in [https://ieeexplore.ieee.org/document/9360308 TCAS-I].