Research - Revision history

Taskin at 15:15, 5 February 2025

2025-02-05T15:15:33Z

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	Drexel VANDAL consists of a research group of computer engineers and electrical engineers tackling big engineering problems of building sophisticated systems. ~~Some of the projects are in:~~		Drexel VANDAL consists of a research group of computer engineers and electrical engineers tackling big engineering problems of building sophisticated systems.
	* Exa-scale computing systems
	* Smart energy/Smart home systems
	* IoT processor design
	* Bio-Implantable systems
	* 5G communication systems
	* Algorithms and software for IoT hardware and software design, including machine learning
	* Unconventional computing using oscillators
	* Perturbation Biology Modeling


	Some project descriptions are as follows.		Some project descriptions are as follows.

Taskin at 15:15, 5 February 2025

2025-02-05T15:15:03Z

← Older revision		Revision as of 11:15, 5 February 2025
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	Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis		Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis



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	Collaborator(s): Ragh Kuttappa (Intel), Vinayak Honkote (Intel)		Collaborator(s): Ragh Kuttappa (Intel), Vinayak Honkote (Intel)


	== Perturbation Biology Modeling==		== Perturbation Biology Modeling==
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	= Previous Projects =		= Previous Projects =



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	Check our Software Release: [[SynchroTrace]]		Check our Software Release: [[SynchroTrace]]



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	Collaborator(s): Bahram Nabet (Photonics), Ioannis Savidis (Circuits and Systems), Naga Kandasamy (HPC), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).		Collaborator(s): Bahram Nabet (Photonics), Ioannis Savidis (Circuits and Systems), Naga Kandasamy (HPC), Lunal Khuon - Drexel Engineering Technology (RF, analog, and biomedical ICs).



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	Collaborator(s): Mark Hempstead (Computer Architecture)		Collaborator(s): Mark Hempstead (Computer Architecture)


	== Clock Skew Scheduling ==		== Clock Skew Scheduling ==
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	Ph.D. Student(s): [[Jianchao Lu]] (graduated)		Ph.D. Student(s): [[Jianchao Lu]] (graduated)


	== Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==		== Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures ==

Taskin at 15:13, 5 February 2025

2025-02-05T15:13:50Z

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	With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.		With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.

	Ph.D. Student(s): [[Ragh Kuttappa]], [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)		Ph.D. Student(s): [[Ragh Kuttappa]] (graduated), [[Ying Teng]] (graduated), [[Vinayak Honkote]] (graduated), [[Ankit More]] (graduated), [[Jianchao Lu]] (graduated)

	Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis		Sponsor(s): National Science Foundation (CCF-0845270), ACM SIGDA, Mosis
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	Sponsor(s): None		Sponsor(s): None

	Collaborator(s): Emre Salman SUNY-Stony Brook, Diane Lim (Penn School of Medicine), Lunal Khuon ~~- Drexel Engineering Technology~~ (RF, analog, and biomedical ICs).		Collaborator(s): Emre Salman SUNY-Stony Brook, Diane Lim (Penn School of Medicine), Lunal Khuon (RF, analog, and biomedical ICs).


	== Unconventional Computing using ~~oscillators~~==		== Unconventional Computing using Oscillators ==

	Unconventional Computing using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.		Unconventional Computing using oscillators, such as mixed-signal/digital CMOS implementations of quantum annealing circuits in Ising and Potts Machines.
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	== Perturbation Biology Modeling==		== Perturbation Biology Modeling==

	~~This research uses algorithmic~~ approaches to ~~assist in the computational processes that identify~~ and predict ~~through machine learning~~ external ~~sources that lead to perturbation~~ in biological systems, a ~~process~~ that ~~is impactful~~ in ~~health sciences~~ and discovery.		The project develops machine learning approaches to evaluate and predict mechanisms of adaptation to external perturbations in biological systems. While providing a new and fundamental understanding of biological systems, we develop and apply the ML tools in the context of a model paradigm, emergence of resistance to targeted drugs. Machine learning toolset is ideal in identifying relationships that are non trivial, leading to deep understanding of dependencies that exist in combinations and in time. With the help of machine learning and data, "target scores" of the potential treatment responses can be determined in increased precision. Simulation of potential treatments can allow researchers to develop novel biological insights related to the adaptive working mechanism of cancer. As a next step, the developed tool can be incorporated with drug discovery related studies. Observing the short and long-term effects of new drug combinations would accelerate the drug discovery procedure. The developed target score prediction model can be used to monitor the effects of proposed drug combinations as well.



	Ph.D. Student(s): Ceyhun Kayan		Ph.D. Student(s): Ceyhun Kayan

Taskin at 15:09, 5 February 2025

2025-02-05T15:09:46Z

Show changes

Taskin: /* Wireless On-Chip Interconnects */

2024-10-15T13:37:56Z

Wireless On-Chip Interconnects

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	Also see our article titled [[WirelessInterconnect\|"What is Wireless Interconnect?"]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.		Also see our article titled [[WirelessInterconnect\|"What is Wireless Interconnect?"]] in the February 2012 edition of the ACM SIGDA newsletter to 3000+ recipients.

	Ph.D. Student(s): ~~Sief Atari,~~ Yilmaz Gonul, Ceyhun Kayan, [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)		Ph.D. Student(s): Yilmaz Gonul, Ceyhun Kayan, Sief Atari (quit), [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)

	Sponsor(s): National Science Foundation (1232164, [[2008629]]), Mosis		Sponsor(s): National Science Foundation (1232164, [[2008629]]), Mosis

	Collaborator(s): Kapil Dandekar (Wireless Systems)		Collaborator(s): Kapil Dandekar (Wireless Communication Systems, Co-PI)

	== Clock Tree/Mesh Synthesis ==		== Clock Tree/Mesh Synthesis ==

Taskin: /* CMP-NoC Co-design */

2022-10-20T14:15:37Z

CMP-NoC Co-design

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	Ph.D. Student(s): [[Karthik Sangaiah]], [[Michael Lui]], [[Vasil Pano]], [[Ankit More]] (graduated)		Ph.D. Student(s): Sief Atari, [[Karthik Sangaiah]] (graduated), [[Michael Lui]], [[Vasil Pano]] (graduated), [[Ankit More]] (graduated)

	Sponsor(s): None		Sponsor(s): None

Taskin: /* GPU System Co-design */

2022-10-20T14:14:58Z

GPU System Co-design

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	Similar to CMP-NoC Design challenges, the co-design of hardware and software on GPU systems is explored. Platform independent dependencies of threads are analyzed on GPUs, leading to the analysis of software and hardware co-design principles.		Similar to CMP-NoC Design challenges, the co-design of hardware and software on GPU systems is explored. Platform independent dependencies of threads are analyzed on GPUs, leading to the analysis of software and hardware co-design principles.

	Ph.D. Student(s): [[Michael Lui]], [[Karthik Sangaiah]]		Ph.D. Student(s): [[Michael Lui]], [[Karthik Sangaiah]] (graduated)

	Sponsor(s): Samsung GRO		Sponsor(s): Samsung GRO

	Collaborator(s): Mark Hempstead (Computer Architecture)		Collaborator(s): Mark Hempstead (Computer Architecture)


	== Clock Skew Scheduling ==		== Clock Skew Scheduling ==

Taskin: /* Energy Efficient Computing with OptoElectronics */

2022-10-20T14:14:42Z

Energy Efficient Computing with OptoElectronics

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	In order to achieve energy efficient computing for systems ranging from datacenters down to mobile electronics, novel devices, techniques, and methodologies are necessary to reduce the terawatts of power consumed by computational devices. We are proposing an effort to bring together researchers from all levels of the device to systems hierarchy (Devices -> Circuits -> Architecture -> Systems -> Data Center) in a vertically integrated approach addressing the (energy) challenges of future computing devices. Our vision is to build upon novel optoelectronic devices capable of computing a bit while consuming attojoules (10E-18 J) of energy, and progress to energy efficient techniques and methodologies for data centers that consume terawatts of power from the electrical grid. Energy efficient innovations at the circuits, systems/interconnect, architecture, and server/mobile/datacenter platform level have the potential to significantly reduce overall power consumption and address this grand challenge in energy needs. Our team is to leverage the energy efficiency of novel optoelectronic elements, and focus research efforts on reducing the total power consumption of electronic devices through energy efficient techniques and methodologies for IC chips, devices, and ultimately data centers that consume terawatts of power from the electrical grid.		In order to achieve energy efficient computing for systems ranging from datacenters down to mobile electronics, novel devices, techniques, and methodologies are necessary to reduce the terawatts of power consumed by computational devices. We are proposing an effort to bring together researchers from all levels of the device to systems hierarchy (Devices -> Circuits -> Architecture -> Systems -> Data Center) in a vertically integrated approach addressing the (energy) challenges of future computing devices. Our vision is to build upon novel optoelectronic devices capable of computing a bit while consuming attojoules (10E-18 J) of energy, and progress to energy efficient techniques and methodologies for data centers that consume terawatts of power from the electrical grid. Energy efficient innovations at the circuits, systems/interconnect, architecture, and server/mobile/datacenter platform level have the potential to significantly reduce overall power consumption and address this grand challenge in energy needs. Our team is to leverage the energy efficiency of novel optoelectronic elements, and focus research efforts on reducing the total power consumption of electronic devices through energy efficient techniques and methodologies for IC chips, devices, and ultimately data centers that consume terawatts of power from the electrical grid.

	Ph.D. Student(s): [[Ragh Kuttappa]]		Ph.D. Student(s): [[Ragh Kuttappa]] (graduated)

	Sponsor(s): None		Sponsor(s): None

Taskin: /* Ultra Low-Power Adiabatic Circuit Design */

2022-10-20T14:14:31Z

Ultra Low-Power Adiabatic Circuit Design

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	In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.		In this project, novel synchronous circuit implementation methodologies of adiabatic logic design are explored. This methodology enables unprecedented low power operation through charge recovery on the logic and the power-clock network. Ultimately, this research will resolve the well-known shortcomings of adiabatic logic, such as the operating frequency, and help improve the energy efficiency and applicability of adiabatic logic families.

	Ph.D. Student(s): [[Leo Filippini]]		Ph.D. Student(s): Yilmaz Gonul, [[Leo Filippini]] (graduated)

	Sponsor(s): None		Sponsor(s): None

Taskin: /* Design and Automation of Low Swing Clocking */

2022-10-20T14:14:09Z

Design and Automation of Low Swing Clocking

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	Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.		Operating the clock network with low swing is one of the techniques that is explored in order to reduce the power consumption attributed to the clock network of an high-performance architecture. Low-swing operation can be adopted at varying levels of a clock tree with different implications. However, low-swing applicability remains limited in practice due to a number of factors including (i) degradation in the skew performance, (ii) degradation in expected power reduction, (iii) degradation in data timing due to slew degradation, (iv) necessitating level shifters of varying sizes, (v) necessitating low-swing FF designs. Furthermore, the automation of low swing clocking has not been addressed. In this research, the effectiveness of exploiting fully/partially low swing clock trees, the design of custom cell blocks needed for low swing operation and the optimal low swing voltage level determination is studied. The design flow is also targeted to be automated in order to address the different performance, architecture and physical constraints.

	Ph.D. Student(s): [[Scott Lerner]], [[Leo Filippini]], [[Can Sitik]] (graduated)		Ph.D. Student(s): [[Scott Lerner]], [[Leo Filippini]] (graduated), [[Can Sitik]] (graduated)

	Sponsor(s): Semiconductor Research Corporation		Sponsor(s): Semiconductor Research Corporation