Scott Lerner - Revision history

Ragh: /* Journals */

2021-02-02T14:09:42Z

Journals

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	== Journals ==		== Journals ==
			# R. Kuttappa, B. Taskin, S. Lerner, and V. Pano, “Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems“, in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), Accepted February 2021.
	# S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572		# S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572
	# S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664		# S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664

Vasil: /* Presentations */

2018-12-24T07:54:44Z

Presentations

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	# “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, International Symposium on VLSI, Bochum, Germany, July 2017.5. “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, System Level Interconnect Prediction, Austin, Texas, June 2017.		# “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, International Symposium on VLSI, Bochum, Germany, July 2017.5. “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, System Level Interconnect Prediction, Austin, Texas, June 2017.
	# “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, International Symposium on Quality Electronic Design, Santa Clara, California, March 2017.		# “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, International Symposium on Quality Electronic Design, Santa Clara, California, March 2017.

	# Enhancements in Low Voltage and High Performance Clock Distribution Networks, SRC Innovation and Intelligent Internet of Things, November 2016.		# Enhancements in Low Voltage and High Performance Clock Distribution Networks, SRC Innovation and Intelligent Internet of Things, November 2016.
	# High-Frequency Clock Tree Synthesis, Drexel STAR Symposium, August 2016.		# High-Frequency Clock Tree Synthesis, Drexel STAR Symposium, August 2016.

Scott: /* Journals */

2018-12-03T16:36:32Z

Journals

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	== Journals ==		== Journals ==
	# S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in		# S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572
	IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572		# S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664
	# S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”,		# S. Lerner, and B.Taskin, “Workload-Aware ASIC Design Considering Lithography Information”, in preparation for submission, 2019.
	in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664
	# S. Lerner, and B.Taskin, “Workload-Aware ASIC Design Considering Lithography Information”, in preparation for
	submission, 2019.

	== Papers ==		== Papers ==

Scott at 16:35, 3 December 2018

2018-12-03T16:35:52Z

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	[[media:Scott_cv.pdf \| Scott Lerner CV (Dec 2018)]]		[[media:Scott_cv.pdf \| Scott Lerner CV (Dec 2018)]]

	== ~~Selected Publications~~ ==		== Journals ==
	# S. Lerner~~, V. Pano, B.Taskin, NoC Router Lifetime Improvement using Per-Port Router Utilization, Proceedings of the International Symposium on Circuit~~ and ~~Systems (ISCAS) 2018.~~		# S. Lerner and B.Taskin, “Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis”, in
	~~# V. Pano, S. Lerner,~~ B.Taskin, ~~Workload-Aware Routing (WAR)~~ for ~~Network-on-Chip Lifetime Improvement~~, ~~Proceedings of the International Symposium~~ on ~~Circuit and Systems~~ (~~ISCAS~~) ~~2018.~~		IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2874572
	~~# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI, presented at International Symposium on Circuits and~~ Systems ~~(ISCAS)~~, ~~May 2017~~.		# S. Lerner, I. Yilmaz, and B.Taskin, “Custard: ASIC Workload-Aware Reliable Design for Multi-core IoT Processors”,
	~~# S~~. ~~Lerner, B~~.~~Taskin, WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS, presented at International Symposium on VLSI (ISVLSI), July 2017~~.		in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2018. doi: 10.1109/TVLSI.2018.2878664
	# S. Lerner, E. ~~Leggett~~, and B.Taskin, ~~Slew-Down~~: ~~Analysis of Slew Relaxation for Low-Impact Clock Buffers, presented at System Level Interconnect Prediction (SLIP) 2017.~~		# S. Lerner, and B.Taskin, “Workload-Aware ASIC Design Considering Lithography Information”, in preparation for
	~~# S. Lerner, B.Taskin, BSST-DME: Slew Merging Region Propagation for Bounded CTS, submitted to International Conference on Computer Aided Design (ICCAD) 2017.~~		submission, 2019.
	~~# S. Lerner, B.Taskin,~~ Workload-Aware ~~ASIC Flow~~ for ~~Lifetime Improvement of~~ Multi-core IoT ~~Processors~~, ~~Proceedings of the International Symposium~~ on ~~Quality Electronic Design~~, ~~March 2017~~.
	~~# C~~. ~~Sitik, W~~. ~~Liu, S. Lerner, E. Salman, and B. Taskin, An Improved Methodology for Low Voltage Gated Clock Tree Synthesis, submitted to International Symposium on Physical Design (ISPD) 2017~~.
	# ~~S. Nilakantan,~~ S. Lerner, ~~M. Hempstead~~ and B. Taskin, ~~Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI~~ Design ~~(VLSIDESIGN)~~, ~~January 2015. '''Best Paper Nominee'''~~
	~~# C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD~~, ~~October 2014~~.

	== ~~Poster Presentations~~ ==		== Papers ==
	# S. Lerner, B. Taskin ~~Enhancements~~ in ~~Low Voltage~~ and ~~High Performance Clock Distribution Networks~~, ~~Poster presented at SRC Innovation~~ and ~~Intelligent Internet~~ of ~~Things~~, ~~Nov. 2016~~.		# S. Lerner and B.Taskin, “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, Proceedings of the IEEE International Green and Sustainable Computing (IGSC) Conference, Oct. 2018.
	# A. ~~Milani~~, S. Lerner, B. Taskin ~~High~~-~~Frequency Clock Tree Synthesis~~, ~~Poster presented at Drexel STAR~~ Symposium, ~~Aug. 2016~~.		# S. Lerner, V. Pano, and B.Taskin, “NoC Router Lifetime Improvement using Per-Port Router Utilization”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
	# R. ~~Farnesi~~, S. Lerner, B. Taskin ~~Internal Node~~ Relaxation for Clock ~~Tree Synthesis~~, ~~Poster presented at Drexel STAR Symposium~~, ~~Aug~~. ~~2016~~.		# V. Pano, S. Lerner, and B.Taskin, “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018.
	# S. Lerner, B. Taskin ~~Workload~~-Aware ~~EDA~~, ~~Presentation given at IEEE CE Graduate~~ Symposium, ~~Feb~~. ~~2016~~.		# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, “Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2017.
	# S. Lerner, V. ~~Pano~~, and B. Taskin, Wireless Network-on-Chip, ~~Poster to be presented at~~ Mid-Atlantic ASEE, November 2014		# S. Lerner and B.Taskin, “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, Proceedings of the International Symposium on VLSI (ISVLSI), Jul. 2017.
	# ~~S. Lerner,~~ Arduino Robotics in the Classroom, ~~Poster to be presented at~~ Mid-Atlantic ASEE, November 2014		# S. Lerner, E. Leggett, and B.Taskin, “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, Proceedings of the System Level Interconnect Prediction (SLIP), Jun. 2017.
	# ~~Scott Lerner, and Baris Taskin,~~ Low-Power Clock Network Designs, ~~Poster presented at~~ IEEE Design Automation Conference, June 2014		# S. Lerner and B.Taskin, “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, Proceedings of the International Symposium on Quality Electronic Design (ISQED), Mar. 2017.
	# ~~S. Lerner, C. Sitik, and B. Taskin,~~ Low Swing Clocking Algorithm for 20nm FinFET Technology, ~~Poster presented at~~ Upsilon Pi Epsilon Research Reception, February 2014.		# S. Nilakantan, S. Lerner, M. Hempstead, and B. Taskin, “Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation”, '''Nominated for best paper''' at the IEEE International Conference on VLSI Design (VLSID), Jan. 2015.
	# ~~S. Lerner, C. Sitik, and B. Taskin,~~ Sub-45nm Interconnect Modeling, ~~Poster presented at~~ Drexel IEEE Graduate Forum, February 2014.		# C. Sitik, S. Lerner, and B. Taskin, “Timing Characterization of Clock Buffers for Clock Tree Synthesis”, Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2014.
	# ~~S. Lerner, R. Welliver, B. Derveni, C. Schoenfield, I. Yilmaz,~~ MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, ~~presented at~~ Philly Codefest, February 2014.
	# ~~C. Sitik, S. Lerner, and B. Taskin,~~ Low-Power/High-Performance Clock Network Design for Microprocessors, ~~Poster presented at~~ Upsilon Pi Epsilon Research Reception, February 2013.		== Presentations ==
			# “Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis”, International Green and Sustainable Computing Conference, Pittsburgh, PA, October 2018.
			# “NoC Router Lifetime Improvement using Per-Port Router Utilization”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
			# “Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement”, International Symposium on Circuit and Systems, Florence, Italy, May 2018.
			# “WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS”, International Symposium on VLSI, Bochum, Germany, July 2017.5. “Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers”, System Level Interconnect Prediction, Austin, Texas, June 2017.
			# “Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors”, International Symposium on Quality Electronic Design, Santa Clara, California, March 2017.

			# Enhancements in Low Voltage and High Performance Clock Distribution Networks, SRC Innovation and Intelligent Internet of Things, November 2016.
			# High-Frequency Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
			# Internal Node Relaxation for Clock Tree Synthesis, Drexel STAR Symposium, August 2016.
			# Workload-Aware EDA, IEEE CE Graduate Symposium, February 2016.
			# Wireless Network-on-Chip, Mid-Atlantic ASEE, November 2014
			# Arduino Robotics in the Classroom, Mid-Atlantic ASEE, November 2014
			# Low-Power Clock Network Designs, IEEE Design Automation Conference, June 2014
			# Low Swing Clocking Algorithm for 20nm FinFET Technology, Upsilon Pi Epsilon Research Reception, February 2014.
			# Sub-45nm Interconnect Modeling, Drexel IEEE Graduate Forum, February 2014.
			# MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014.
			# Low-Power/High-Performance Clock Network Design for Microprocessors, Upsilon Pi Epsilon Research Reception, February 2013.

	== Awards ==		== Awards ==
			# IGSC Best Presentation Nominee, 2018
			# IGSC Travel Award, 2018
			# Weggel Family Fellowship, 2018
	# Frank and Agnes Seaman Endowed Fellowship, 2016		# Frank and Agnes Seaman Endowed Fellowship, 2016
	# NSF Graduate Research Fellowship Program (GRFP), 2015		# NSF Graduate Research Fellowship Program (GRFP), 2015-2018
	# National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015		# National Defense Science & Engineering Graduate (NDSEG) Fellowship (declined), 2015
	# Nihat Bilgutay Award, 2015		# Nihat Bilgutay Award, 2015
	# TCVLSI Travel Award, 2015		# TCVLSI Travel Award, 2015
	# NSF Research Experience for Undergraduate (REU) recipient 2014		# NSF Research Experience for Undergraduate (REU) recipient 2014
	# A. Richard Newton Young Fellow Award ~~to attend to IEEE/ACM DAC~~ 2014, 2015, 2016, 2017		# A. Richard Newton Young Fellow Award 2014, 2015, 2016, 2017, 2018
	# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA		# Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
	# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA		# NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
	# Doctor Thomas Moore Endowed Grant 2014		# Doctor Thomas Moore Endowed Grant 2014
	# Dean's List, 2009~~, 2010, 2011, 2012, 2013,~~ 2014		# Dean's List, 2009-2014

	== Selected Projects ==		== Selected Projects ==

Scott: /* Curriculum Vitae */

2018-12-03T16:04:58Z

Curriculum Vitae

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	== Curriculum Vitae ==		== Curriculum Vitae ==
	[[media:~~Scott_CV_v11~~.pdf \| Scott Lerner CV (~~Jun~~ 2018)]]		[[media:Scott_cv.pdf \| Scott Lerner CV (Dec 2018)]]

	== Selected Publications ==		== Selected Publications ==

Scott: /* Research Interests */

2018-12-03T16:03:20Z

Research Interests

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	== Research Interests ==		== Research Interests ==
	* My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging		My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging
	computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and		computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and
	internet-of-things.		internet-of-things.

Scott: /* Research Interests */

2018-12-03T16:03:08Z

Research Interests

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	== Research Interests ==		== Research Interests ==
	* ~~Physical Design including Floorplanning~~, ~~Placement~~ and ~~Routing~~		* My research interests span the areas of circuits and systems, computer architecture, cross-layer techniques, and emerging
	* Interconnect Modeling		computing systems. I have specific interests in workload-awareness, machine learning, multi-core architectures, and
	* Parametric on-~~chip Variation~~		internet-of-things.
	* Low-~~power Clock Tree Topologies~~
	* Low-~~power Clock Gating~~
	* Software Analysis for Hardware Reliability

	== Curriculum Vitae ==		== Curriculum Vitae ==

Scott: /* Education */

2018-12-03T16:01:54Z

Education

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	== Education ==		== Education ==
	'''PhD in Electrical Engineering expected graduation ~~2018~~''' <br>		'''PhD in Electrical Engineering expected graduation mid-2019''' <br>
	:Drexel University, Philadelphia, PA.		:Drexel University, Philadelphia, PA.
	'''B.S. in Electrical Engineering, 2014''' <br>		'''B.S. in Electrical Engineering, 2014''' <br>

Scott: /* Selected Publications */

2018-07-02T15:08:50Z

Selected Publications

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	== Selected Publications ==		== Selected Publications ==
	# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI, ~~to be~~ presented at International Symposium on Circuits and Systems (ISCAS), May 2017.		# S. Lerner, V. Pano, B.Taskin, NoC Router Lifetime Improvement using Per-Port Router Utilization, Proceedings of the International Symposium on Circuit and Systems (ISCAS) 2018.
	# S. Lerner, B.Taskin, WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS, ~~to be~~ presented at International Symposium on VLSI (ISVLSI), July 2017.		# V. Pano, S. Lerner, B.Taskin, Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement, Proceedings of the International Symposium on Circuit and Systems (ISCAS) 2018.
	# S. Lerner, E. Leggett, and B.Taskin, Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers, ~~to be~~ presented at System Level Interconnect Prediction (SLIP) 2017.		# R.Kuttappa, L. Fillipini, S. Lerner, and B.Taskin, Stability of Rotary Traveling Wave Oscillators under Process Variations and NBTI, presented at International Symposium on Circuits and Systems (ISCAS), May 2017.
			# S. Lerner, B.Taskin, WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type for CTS, presented at International Symposium on VLSI (ISVLSI), July 2017.
			# S. Lerner, E. Leggett, and B.Taskin, Slew-Down: Analysis of Slew Relaxation for Low-Impact Clock Buffers, presented at System Level Interconnect Prediction (SLIP) 2017.
	# S. Lerner, B.Taskin, BSST-DME: Slew Merging Region Propagation for Bounded CTS, submitted to International Conference on Computer Aided Design (ICCAD) 2017.		# S. Lerner, B.Taskin, BSST-DME: Slew Merging Region Propagation for Bounded CTS, submitted to International Conference on Computer Aided Design (ICCAD) 2017.
	# S. Lerner, B.Taskin, Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors, Proceedings of the International Symposium on Quality Electronic Design, March 2017.		# S. Lerner, B.Taskin, Workload-Aware ASIC Flow for Lifetime Improvement of Multi-core IoT Processors, Proceedings of the International Symposium on Quality Electronic Design, March 2017.

Scott: /* Curriculum Vitae */

2018-06-06T14:08:25Z

Curriculum Vitae

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	== Curriculum Vitae ==		== Curriculum Vitae ==
	[[media:~~Scott_CV_v8~~.pdf \| Scott Lerner CV (Jun ~~2017~~)]]		[[media:Scott_CV_v11.pdf \| Scott Lerner CV (Jun 2018)]]

	== Selected Publications ==		== Selected Publications ==