WirelessInterconnect - Revision history

Taskin at 14:55, 3 February 2012

2012-02-03T14:55:10Z

← Older revision		Revision as of 10:55, 3 February 2012
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	=What is Wireless On-Chip Interconnect?=		=What is Wireless On-Chip Interconnect?=
	~~Ankit More and Baris Taskin~~

	~~Drexel University~~

	~~----~~

	Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:		Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:

Taskin at 14:52, 3 February 2012

2012-02-03T14:52:47Z

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	[[File:sigdafeb12.~~jpg~~]]		[[File:sigdafeb12.png]]

	=What is Wireless On-Chip Interconnect?=		=What is Wireless On-Chip Interconnect?=

Taskin at 14:51, 3 February 2012

2012-02-03T14:51:32Z

← Older revision		Revision as of 10:51, 3 February 2012
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	Ankit More and Baris Taskin		Ankit More and Baris Taskin

	~~http://vlsi.ece.drexel.edu~~		Drexel University

	~~Drexel University~~
	----		----

	Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:		Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:

Taskin at 14:51, 3 February 2012

2012-02-03T14:51:09Z

← Older revision		Revision as of 10:51, 3 February 2012
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	Drexel University		Drexel University
			----
	Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:		Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:

Taskin at 14:50, 3 February 2012

2012-02-03T14:50:16Z

← Older revision		Revision as of 10:50, 3 February 2012
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	=What is Wireless On-Chip Interconnect?=		=What is Wireless On-Chip Interconnect?=
	Ankit More and Baris Taskin		Ankit More and Baris Taskin
	[http://vlsi.ece.drexel.edu]
			http://vlsi.ece.drexel.edu

	Drexel University		Drexel University

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	[7] D. Zhao and Y. Wang, "SD-MAC: Design and Synthesis of a Hardware- Efficient Collision-free QoS-aware MAC Protocol for Wireless Network-on- chip," IEEE Transactions on Computers, vol. 57, pp. 1230-1245, 2008.		[7] D. Zhao and Y. Wang, "SD-MAC: Design and Synthesis of a Hardware- Efficient Collision-free QoS-aware MAC Protocol for Wireless Network-on- chip," IEEE Transactions on Computers, vol. 57, pp. 1230-1245, 2008.

	[8] A. More and B. Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs,"Â IEEE International Conference on Computer Design (ICCD), 2011, pp. 19-24.		[8] A. More and B. Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs," IEEE International Conference on Computer Design (ICCD), 2011, pp. 19-24.

	[9] A. B. M. H. Rashid et al., "Interference Suppression of Wireless Interconnection in Si Integrated Antenna," IEEE International Interconnect Technology Conference (IITC), 2002, pp. 173-175.		[9] A. B. M. H. Rashid et al., "Interference Suppression of Wireless Interconnection in Si Integrated Antenna," IEEE International Interconnect Technology Conference (IITC), 2002, pp. 173-175.

Taskin at 14:48, 3 February 2012

2012-02-03T14:48:57Z

Taskin at 14:47, 3 February 2012

2012-02-03T14:47:10Z

← Older revision		Revision as of 10:47, 3 February 2012
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	; P-1) Information Networking Paradigm: The information networking paradigm considers higher level hybrid architectural design variables:		; P-1) Information Networking Paradigm: The information networking paradigm considers higher level hybrid architectural design variables:

	~~(a)~~ the architecture of the hybrid NoC using the wireless interconnects,		## the architecture of the hybrid NoC using the wireless interconnects,

	~~(b)~~ the number of wireless nodes and the arbitration protocol,		## the number of wireless nodes and the arbitration protocol,

	~~(c)~~ the placement of the wireless nodes in a given network topology constrained to the maximum possible communication distance,		## the placement of the wireless nodes in a given network topology constrained to the maximum possible communication distance,

	~~(d)~~ the protocol to select the wireless short-cut path over the wired path.		## the protocol to select the wireless short-cut path over the wired path.

	It is proposed in [6], for instance, that the entire network be broken up into subnets of computational cores with top-level hubs connected with wireless ports for the high speed links conforming to a small-world topology. Protocols for a collision free and quality of service (QoS)-aware hybrid wireless NoCs, in presence of multiple antennas at the same carrier frequency, are presented in [7].		It is proposed in [6], for instance, that the entire network be broken up into subnets of computational cores with top-level hubs connected with wireless ports for the high speed links conforming to a small-world topology. Protocols for a collision free and quality of service (QoS)-aware hybrid wireless NoCs, in presence of multiple antennas at the same carrier frequency, are presented in [7].

Taskin at 14:46, 3 February 2012

2012-02-03T14:46:22Z

Taskin at 14:45, 3 February 2012

2012-02-03T14:45:32Z

← Older revision		Revision as of 10:45, 3 February 2012
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	Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:		Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:

	1. On-chip micro-strip transmission lines [1],		# On-chip micro-strip transmission lines [1],
			# On-chip antennas [2],
	2. On-chip antennas [2],		# On-chip inductors based inductive coupling [3],
			#On-chip capacitors based capacitive coupling [4].
	3. On-chip inductors based inductive coupling [3],

	4. On-chip capacitors based capacitive coupling [4].

	The micro-strip lines are used as guided-wave RF interconnects (RF-I[1]) on a layer for lateral communication whereas the other three are configured as wireless RF interconnects used for lateral or vertical communication.		The micro-strip lines are used as guided-wave RF interconnects (RF-I[1]) on a layer for lateral communication whereas the other three are configured as wireless RF interconnects used for lateral or vertical communication.

Taskin at 14:44, 3 February 2012

2012-02-03T14:44:38Z

Show changes

← Older revision		Revision as of 10:48, 3 February 2012
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	[[File:sigdafeb12.jpg]]		[[File:sigdafeb12.jpg]]

	~~'''~~What is Wireless On-Chip Interconnect?~~'''~~		=What is Wireless On-Chip Interconnect?=
	Ankit More and Baris Taskin		Ankit More and Baris Taskin
	[http://vlsi.ece.drexel.edu]		[http://vlsi.ece.drexel.edu]
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	; P-1) Information Networking Paradigm: The information networking paradigm considers higher level hybrid architectural design variables:		; P-1) Information Networking Paradigm: The information networking paradigm considers higher level hybrid architectural design variables:

	## the architecture of the hybrid NoC using the wireless interconnects,		:: (a) the architecture of the hybrid NoC using the wireless interconnects,

	## the number of wireless nodes and the arbitration protocol,		:: (b) the number of wireless nodes and the arbitration protocol,

	## the placement of the wireless nodes in a given network topology constrained to the maximum possible communication distance,		:: (c) the placement of the wireless nodes in a given network topology constrained to the maximum possible communication distance,

	## the protocol to select the wireless short-cut path over the wired path.		:: (d) the protocol to select the wireless short-cut path over the wired path.

	It is proposed in [6], for instance, that the entire network be broken up into subnets of computational cores with top-level hubs connected with wireless ports for the high speed links conforming to a small-world topology. Protocols for a collision free and quality of service (QoS)-aware hybrid wireless NoCs, in presence of multiple antennas at the same carrier frequency, are presented in [7].		It is proposed in [6], for instance, that the entire network be broken up into subnets of computational cores with top-level hubs connected with wireless ports for the high speed links conforming to a small-world topology. Protocols for a collision free and quality of service (QoS)-aware hybrid wireless NoCs, in presence of multiple antennas at the same carrier frequency, are presented in [7].
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	; P-2) Physical Implementation Paradigm: The physical implementation paradigm considers both the antenna design and the transceiver design. The antenna and the transceiver design depend on:		; P-2) Physical Implementation Paradigm: The physical implementation paradigm considers both the antenna design and the transceiver design. The antenna and the transceiver design depend on:

	(a) the carrier frequency and the required bandwidth,		:: (a) the carrier frequency and the required bandwidth,

	(b) the maximum communication distance,		:: (b) the maximum communication distance,

	(c) the maximum power dissipation,		:: (c) the maximum power dissipation,

	(d) the output power of the transmitter and sensitivity of the receiver,		:: (d) the output power of the transmitter and sensitivity of the receiver,

	(e) the electro-magnetic compatibility (EMC) and the electro-magnetic interference (EMI) of the wireless system with the other on-chip elements.		:: (e) the electro-magnetic compatibility (EMC) and the electro-magnetic interference (EMI) of the wireless system with the other on-chip elements.

	A silicon implementation of a wireless interconnects system at 15GHz is presented in [2]. Dynamic reconfiguration of the wireless links between multiple frequencies is proposed in [8]. Design guidelines for reducing the impact of on-chip metal structures (i.e. interconnects and vias) on the performance and characteristics of the on-chip antennas are provided in [9].		A silicon implementation of a wireless interconnects system at 15GHz is presented in [2]. Dynamic reconfiguration of the wireless links between multiple frequencies is proposed in [8]. Design guidelines for reducing the impact of on-chip metal structures (i.e. interconnects and vias) on the performance and characteristics of the on-chip antennas are provided in [9].
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	; P-3) Wireless Communication Paradigm: The wireless communication paradigm models the communication channel. It provides the model for the path loss between the antenna pair and the signal to noise ratio (SNR) requirement based on the required bit-error-rate (BER) from the wireless communication channel. The SNR places constraints on:		; P-3) Wireless Communication Paradigm: The wireless communication paradigm models the communication channel. It provides the model for the path loss between the antenna pair and the signal to noise ratio (SNR) requirement based on the required bit-error-rate (BER) from the wireless communication channel. The SNR places constraints on:

	(a) the maximum wirelessly communicable distance,		:: (a) the maximum wirelessly communicable distance,

	(b) the required output power from the transmitter,		:: (b) the required output power from the transmitter,

	(c) the required sensitivity of the receiver.		:: (c) the required sensitivity of the receiver.

	These constraints in turn determine the power requirements of the transceiver. The SNR requirement can be eased by utilizing error-correction coding (ECC).		These constraints in turn determine the power requirements of the transceiver. The SNR requirement can be eased by utilizing error-correction coding (ECC).

← Older revision		Revision as of 10:46, 3 February 2012
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	# On-chip antennas [2],		# On-chip antennas [2],
	# On-chip inductors based inductive coupling [3],		# On-chip inductors based inductive coupling [3],
	#On-chip capacitors based capacitive coupling [4].		# On-chip capacitors based capacitive coupling [4].

	The micro-strip lines are used as guided-wave RF interconnects (RF-I[1]) on a layer for lateral communication whereas the other three are configured as wireless RF interconnects used for lateral or vertical communication.		The micro-strip lines are used as guided-wave RF interconnects (RF-I[1]) on a layer for lateral communication whereas the other three are configured as wireless RF interconnects used for lateral or vertical communication.
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	The wireless interconnects are not envisioned to antiquate the metal based interconnects but rather to be implemented in conjunction to provide hybrid communication structures and networks-on-chip (NoC), particularly for 2D or 3D multi-processor system-on-chips (MPSoCs). The design of the wireless RF interconnects for all systems in general but for multi-core systems in particular requires considerations across a vast variety of subjects including, electro-magnetic theory, network theory, wireless communication, VLSI design and design automation. The multi-faceted design considerations are categorized according to three primary design paradigms [5]:		The wireless interconnects are not envisioned to antiquate the metal based interconnects but rather to be implemented in conjunction to provide hybrid communication structures and networks-on-chip (NoC), particularly for 2D or 3D multi-processor system-on-chips (MPSoCs). The design of the wireless RF interconnects for all systems in general but for multi-core systems in particular requires considerations across a vast variety of subjects including, electro-magnetic theory, network theory, wireless communication, VLSI design and design automation. The multi-faceted design considerations are categorized according to three primary design paradigms [5]:

	P-1) Information Networking Paradigm: The information networking paradigm considers higher level hybrid architectural design variables:		; P-1) Information Networking Paradigm: The information networking paradigm considers higher level hybrid architectural design variables:

	(a) the architecture of the hybrid NoC using the wireless interconnects,		(a) the architecture of the hybrid NoC using the wireless interconnects,
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	It is proposed in [6], for instance, that the entire network be broken up into subnets of computational cores with top-level hubs connected with wireless ports for the high speed links conforming to a small-world topology. Protocols for a collision free and quality of service (QoS)-aware hybrid wireless NoCs, in presence of multiple antennas at the same carrier frequency, are presented in [7].		It is proposed in [6], for instance, that the entire network be broken up into subnets of computational cores with top-level hubs connected with wireless ports for the high speed links conforming to a small-world topology. Protocols for a collision free and quality of service (QoS)-aware hybrid wireless NoCs, in presence of multiple antennas at the same carrier frequency, are presented in [7].

	P-2) Physical Implementation Paradigm: The physical implementation paradigm considers both the antenna design and the transceiver design. The antenna and the transceiver design depend on:		; P-2) Physical Implementation Paradigm: The physical implementation paradigm considers both the antenna design and the transceiver design. The antenna and the transceiver design depend on:

	(a) the carrier frequency and the required bandwidth,		(a) the carrier frequency and the required bandwidth,
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	A silicon implementation of a wireless interconnects system at 15GHz is presented in [2]. Dynamic reconfiguration of the wireless links between multiple frequencies is proposed in [8]. Design guidelines for reducing the impact of on-chip metal structures (i.e. interconnects and vias) on the performance and characteristics of the on-chip antennas are provided in [9].		A silicon implementation of a wireless interconnects system at 15GHz is presented in [2]. Dynamic reconfiguration of the wireless links between multiple frequencies is proposed in [8]. Design guidelines for reducing the impact of on-chip metal structures (i.e. interconnects and vias) on the performance and characteristics of the on-chip antennas are provided in [9].

	P-3) Wireless Communication Paradigm: The wireless communication paradigm models the communication channel. It provides the model for the path loss between the antenna pair and the signal to noise ratio (SNR) requirement based on the required bit-error-rate (BER) from the wireless communication channel. The SNR places constraints on:		; P-3) Wireless Communication Paradigm: The wireless communication paradigm models the communication channel. It provides the model for the path loss between the antenna pair and the signal to noise ratio (SNR) requirement based on the required bit-error-rate (BER) from the wireless communication channel. The SNR places constraints on:

	(a) the maximum wirelessly communicable distance,		(a) the maximum wirelessly communicable distance,