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=What is Wireless On-Chip Interconnect?=

Wireless on-chip interconnects are a radio-frequency (RF) alternative to metal interconnects for global communication on an IC. RF interconnect channels are based on:

# On-chip micro-strip transmission lines [1],
# On-chip antennas [2],
# On-chip inductors based inductive coupling [3],
# On-chip capacitors based capacitive coupling [4].

The micro-strip lines are used as guided-wave RF interconnects (RF-I[1]) on a layer for lateral communication whereas the other three are configured as wireless RF interconnects used for lateral or vertical communication.

The wireless interconnects are not envisioned to antiquate the metal based interconnects but rather to be implemented in conjunction to provide hybrid communication structures and networks-on-chip (NoC), particularly for 2D or 3D multi-processor system-on-chips (MPSoCs). The design of the wireless RF interconnects for all systems in general but for multi-core systems in particular requires considerations across a vast variety of subjects including, electro-magnetic theory, network theory, wireless communication, VLSI design and design automation. The multi-faceted design considerations are categorized according to three primary design paradigms [5]:

; P-1) Information Networking Paradigm: The information networking paradigm considers higher level hybrid architectural design variables:

:: (a) the architecture of the hybrid NoC using the wireless interconnects,

:: (b) the number of wireless nodes and the arbitration protocol,

:: (c) the placement of the wireless nodes in a given network topology constrained to the maximum possible communication distance,

:: (d) the protocol to select the wireless short-cut path over the wired path.

It is proposed in [6], for instance, that the entire network be broken up into subnets of computational cores with top-level hubs connected with wireless ports for the high speed  links conforming to a small-world topology. Protocols for a collision free and quality of service (QoS)-aware hybrid wireless NoCs, in presence of multiple antennas at the same carrier frequency, are presented in [7].

; P-2) Physical Implementation Paradigm: The physical implementation paradigm considers both the antenna design and the transceiver design. The antenna and the transceiver design depend on:

:: (a) the carrier frequency and the required bandwidth,

:: (b) the maximum communication distance,

:: (c) the maximum power dissipation,

:: (d) the output power of the transmitter and sensitivity of the receiver,

:: (e) the electro-magnetic compatibility (EMC) and the electro-magnetic interference (EMI) of the wireless system with the other on-chip elements.

A silicon implementation of a wireless interconnects system at 15GHz is presented in [2]. Dynamic reconfiguration of the wireless links between multiple frequencies is proposed in [8]. Design guidelines for reducing the impact of on-chip metal structures (i.e. interconnects and vias) on the performance and characteristics of the on-chip antennas are provided in [9].

; P-3) Wireless Communication Paradigm: The wireless communication paradigm models the communication channel. It provides the model for the path loss between the antenna pair and the signal to noise ratio (SNR) requirement based on the required bit-error-rate (BER) from the wireless communication channel. The SNR places constraints on:

:: (a) the maximum wirelessly communicable distance,

:: (b) the required output power from the transmitter,

:: (c) the required sensitivity of the receiver.

These constraints in turn determine the power requirements of the transceiver. The SNR requirement can be eased by utilizing error-correction coding (ECC).

The wireless interconnect channel is modeled and characterized for the path loss and delay spread in [10] and the BER and SNR for the wireless interconnect system are analyzed in [11] and [12], respectively.

In summary, the design of the hybrid NoC architectures using wireless on-chip interconnects can potentially provide high throughput and energy savings in 2D and 3D MPSoCs. However, their adaptability and benefits depend on the integration of the multiple facets involved in the design of such complex systems.

References

[1] M. F. Chang, V. P. Roychowdhury, L. Zhang, H. Shin and Y. Qian, "RF/Wireless Interconnect for Inter- and Intra-chip Communications," Proceedings of the IEEE, vol. 89, pp. 456-466, April 2001.

[2] B. A. Floyd, C.-M. Hung and K.K. O, "Intra-chip Wireless Interconnect for Clock Distribution Implemented with Integrated Antennas, Receivers and Transmitters," IEEE Journal of Solid-State Circuits, vol. 37, pp. 543-551, May 2002.

[3] N. Miura et al., "A 0.14pJ/b inductive-coupling transceiver with digitally-controlled precise pulse shaping," IEEE Journal of Solid-State Circuits, pp. 285-291, January 2008.

[4] A. Fazzi et al., "3D capacitive interconnections with mono- and bi- directional capabilities," IEEE Journal of Solid-State Circuits, pp. 275-284, January 2008.

[5] A. More and B. Taskin, "A Unified Design Methodology for a Hybrid Wireless 2-D NoC," IEEE International Symposium on Circuits and Systems (ISCAS), 2012.

[6] S. Deb, A. Ganguly, K. Chang, P. Pande, B. Beizer, and D. Heo, "Enhancing Performance of Network-on-chip Architectures with Millimeter-wave Wireless Interconnects," IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010, pp. 73-80.

[7] D. Zhao and Y. Wang, "SD-MAC: Design and Synthesis of a Hardware- Efficient Collision-free QoS-aware MAC Protocol for Wireless Network-on- chip," IEEE Transactions on Computers, vol. 57, pp. 1230-1245, 2008.

[8] A. More and B. Taskin, "EM and Circuit Co-simulation of a Reconfigurable Hybrid Wireless NoC on 2D ICs," IEEE International Conference on Computer Design (ICCD), 2011, pp. 19-24.

[9] A. B. M. H. Rashid et al., "Interference Suppression of Wireless Interconnection in Si Integrated Antenna," IEEE International Interconnect Technology Conference (IITC), 2002, pp. 173-175.

[10] M. Sun, Y. P. Zhang, G. X. Zheng, and W. Y. Yin, "Performance of intra-chip wireless interconnect using on-chip antennas and UWB radios," IEEE Transactions on Antennas and Propagation, vol. 57, pp. 2756-2762, September 2009.

[11] Y. P. Zhang, "Bit-error-rate Performance of Intra-chip Wireless Interconnect Systems," IEEE Communications Letters, vol. 8, pp. 39-41, January 2004.

[12] D. Bravo et al., "Estimation of the Signal-to-noise Ratio for On-chip Wireless Clock Signal Distribution," IEEE International Interconnect Technology Conference (IITC), 2000, pp. 9-11.