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[[Research#CMP-NoC Co-design|CMP-NoC Co-design]] | [[Research#CMP-NoC Co-design|CMP-NoC Co-design]] | ||
[[Research#Embedded System Co-design|Embedded System Co-design]] | [[Research#GPU/Embedded System Co-design|Embedded System Co-design]] | ||
[[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]] | [[Research#Design and Automation of Low Swing Clocking|Design and Automation of Low Swing Clocking]] | ||
Revision as of 09:59, 16 June 2015
Drexel VLSI and Architecture Laboratory (http://vlsi.ece.drexel.edu)
Department of Electrical and Computer Engineering
324 Bossone Research Center
Philadelphia, PA 19104
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Research
Design and Automation of Low Swing Clocking
Wireless On-Chip Interconnects
Ultra Low-Power Adiabatic Circuit Design
