Software: Difference between revisions

From VLSILab
Jump to navigationJump to search
No edit summary
No edit summary
Line 6: Line 6:
[[SLECTS]]
[[SLECTS]]


A slew-driven clock tree synthesis methodology.
Implementing a slew-driven clock tree synthesis methodology.




[[Rotary Automator]]
[[Rotary Resonant Clock Synthesizer]]


A rotary resonant clock synthesizer in Cadence.
A rotary resonant clock synthesizer in Cadence.

Revision as of 22:42, 29 January 2016

SynchroTrace

SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of CMPs.


SLECTS

Implementing a slew-driven clock tree synthesis methodology.


Rotary Resonant Clock Synthesizer

A rotary resonant clock synthesizer in Cadence.