|
|
| (19 intermediate revisions by 2 users not shown) |
| Line 1: |
Line 1: |
| '''Topic Outline'''
| | Content moved to: |
|
| |
|
| Trace capture & analysis for multi-threaded programs, large design space exploration, and insights from workload profiling (e.g. accelerator design via hw/sw co-design and related architectural decisions).
| | [[Tutorials:SynchroTrace Sigil ICCD 2015]] |
|
| |
|
| '''Synopsis'''
| | [[Tutorials:SynchroTrace Sigil IISWC 2015]] |
| | |
| The [[SynchroTrace]] simulation framework enables exploration of a large design space. It has demonstrated speed and accuracy in aiding uncore designers for cache and network-on-chip design decisions, and is currently being integrated into Gem5 as an official patch.
| |
| | |
| [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil] is our workload profiling toolset that has enabled SynchroTrace. It captures and classifies a workload's computation and communication operations, and intercepts synchronization actions within threads. Sigil has been used for accelerator co-design research by gathering communication edges between functions/threads to provide insight to the ''true'' cost of a workload. Additionally, its unique ability to create non-deterministic traces in a multithreaded trace is utilized for truly architecture-agnostic simulations.
| |
| | |
| '''Agenda'''
| |
| | |
| In this talk we discuss the utility and impact of SynchroTrace and Sigil, and show examples downloading, building, and running the tools, along with analysis of the data produced.
| |
Latest revision as of 10:27, 26 August 2016
