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== Vertically Integrated Projects (VIP) at Drexel University == | |||
'''IoT Processor Team''' by Prof. Taskin | |||
The goal of this VIP team is to investigate software and hardware design methods to design low-power, high performance computing elements such as processors, application-specific integrated circuits and systems-on-chip. The processors are intended for a wide range of applications from cloud servers to mobile handsets but the particular intend is to build processors for the emerging applications of Internet of Things (IoT) and edge computing, and primarily perform exa-scale computing workloads at such small footprints of area and energy. | |||
Apply through Drexel Discover website of Drexel Office of Undergraduate Research. | |||
== Outreach == | |||
An NSF-funded Research Experience for Undergraduates (REU) Site (2010-2012) on "Computing for Power and Energy" directed by Dr. Taskin: [http://reu.ece.drexel.edu REU Site on Computing for Power and Energy: The Old, The New and The Renewable]. | |||
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File:DrexelREU2010web.jpg | |||
</gallery> | |||
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MS in VLSI in the US at Drexel University [[media:Drexel_MS_in_VLSI.pdf|Promotional Material]] (May 2017) | |||
== Courses == | == Courses == | ||
ECE- | ECE-C471 Custom VLSI Design | ||
ECE-C474 ASIC Design I | |||
ECE-C475 ASIC Design II | |||
ECE-C671 EDA for VLSI Design I | |||
ECE-C672 EDA for VLSI Design II | |||
ECE-C673 Deep Sub-Micron (DSM) IC Design | |||
ECE-C690 Special Topics: Network on Chip | |||
Occasionally teach these courses as well: | |||
ENGR 121 Computation Lab I | |||
ENGR 122 Computation Lab II | |||
ENGR 231 Linear Engineering Systems | |||
ENGR 232 Dynamic Engineering Systems | |||
ECE- | ECE-C304 Design with Microcontrollers | ||
ECE- | ECE-C356 Embedded Systems | ||
ECE 200 Digital Logic Systems | |||
== Senior Design == | == Senior Design == | ||
===Academic Year 2016-2017 === | |||
* "ArchEval, an Application for Architectural Evaluation" | |||
Avik Bag, Eric Rock, George Slavin | |||
* "Wireless System for Measuring Neural Physiological Data in Brain Tissue" | |||
Darshan Donthi, Anthony Romano, Scott Szybist | |||
===Academic Year 2015-2016 === | |||
* "Wireless DRAM Solution" | |||
David Hong, Isikcan Yilmaz, Stephen Yohannan | |||
===Academic Year 2013-2014 === | |||
* "Hybrid Wireless Network-on-Chip System" | |||
Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano | |||
ASEE Mid-Atlantic Section Conference 2014 Poster presentation | |||
=== Academic Year 2012-2013 === | |||
* ''Assisted Living Monitoring System'' | |||
Members: Jeffrey Eckert, Neev Wanvari | |||
=== Academic Year 2010-2011 === | |||
* ''Ultra Low Power Full-Adder IC Design'' | |||
Members: Kevin Daly, Tiffany Lakins, Ramen Tieu | |||
=== Academic Year 2009-2010 === | |||
* ''Scalability of Rotary Traveling-Wave Oscillators'' | |||
Members: Eric Fargnoli, Colby Weingarten | |||
Drexel ECE Senior Design Award - Computer Engineering | |||
=== Academic Year 2008-2009 === | === Academic Year 2008-2009 === | ||
* ''Internetworked Nanowire Sensor Platform'' (co-advised with Dr. Nabet) | * ''Design of and Addressable Internetworked Nanowire Sensor Platform'' (co-advised with Dr. Nabet) | ||
Members: Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak | |||
Fabricated a 1.5x1.5 mm chip in AMI 0.5um technology | |||
Publication: | |||
# K. Yencha, M. Zofchak, D. Oakum, G. Strait, B. Taskin, B. Nabet, "Design of an Addressable Internetworked Microscale Sensor", Special Issue: Journal of Selected Areas in Microelectronics (JSAM), December 2010. | |||
| Line 45: | Line 141: | ||
#Baris Taskin, A. Chiu, J. Salkind, D. Venutolo, A Shift-Register Based QCA Memory Architecture, ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009. | #Baris Taskin, A. Chiu, J. Salkind, D. Venutolo, A Shift-Register Based QCA Memory Architecture, ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009. | ||
# | #Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Ventutolo, A Shift-Register Based QCA Memory Architecture, Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), October 2007, pp. 54--61. | ||
* ''Realizing Arbitrary Boolean Functions with Analog Threshold Logic Circuits'' (co-advised with Dr. Katz) | * ''Realizing Arbitrary Boolean Functions with Analog Threshold Logic Circuits'' (co-advised with Dr. Katz) | ||
| Line 61: | Line 158: | ||
* ''Automated Implementation of Logical Effort'' | * ''Automated Implementation of Logical Effort'' | ||
Members: | Members: David Dimm, Roshani Patel | ||
Latest revision as of 14:55, 27 February 2018
Vertically Integrated Projects (VIP) at Drexel University
IoT Processor Team by Prof. Taskin
The goal of this VIP team is to investigate software and hardware design methods to design low-power, high performance computing elements such as processors, application-specific integrated circuits and systems-on-chip. The processors are intended for a wide range of applications from cloud servers to mobile handsets but the particular intend is to build processors for the emerging applications of Internet of Things (IoT) and edge computing, and primarily perform exa-scale computing workloads at such small footprints of area and energy.
Apply through Drexel Discover website of Drexel Office of Undergraduate Research.
Outreach
An NSF-funded Research Experience for Undergraduates (REU) Site (2010-2012) on "Computing for Power and Energy" directed by Dr. Taskin: REU Site on Computing for Power and Energy: The Old, The New and The Renewable.
MS in VLSI in the US at Drexel University Promotional Material (May 2017)
Courses
ECE-C471 Custom VLSI Design
ECE-C474 ASIC Design I
ECE-C475 ASIC Design II
ECE-C671 EDA for VLSI Design I
ECE-C672 EDA for VLSI Design II
ECE-C673 Deep Sub-Micron (DSM) IC Design
ECE-C690 Special Topics: Network on Chip
Occasionally teach these courses as well:
ENGR 121 Computation Lab I
ENGR 122 Computation Lab II
ENGR 231 Linear Engineering Systems
ENGR 232 Dynamic Engineering Systems
ECE-C304 Design with Microcontrollers
ECE-C356 Embedded Systems
ECE 200 Digital Logic Systems
Senior Design
Academic Year 2016-2017
- "ArchEval, an Application for Architectural Evaluation"
Avik Bag, Eric Rock, George Slavin
- "Wireless System for Measuring Neural Physiological Data in Brain Tissue"
Darshan Donthi, Anthony Romano, Scott Szybist
Academic Year 2015-2016
- "Wireless DRAM Solution"
David Hong, Isikcan Yilmaz, Stephen Yohannan
Academic Year 2013-2014
- "Hybrid Wireless Network-on-Chip System"
Gjergji Konica, Katie Leis, Scott Lerner, Vasil Pano
ASEE Mid-Atlantic Section Conference 2014 Poster presentation
Academic Year 2012-2013
- Assisted Living Monitoring System
Members: Jeffrey Eckert, Neev Wanvari
Academic Year 2010-2011
- Ultra Low Power Full-Adder IC Design
Members: Kevin Daly, Tiffany Lakins, Ramen Tieu
Academic Year 2009-2010
- Scalability of Rotary Traveling-Wave Oscillators
Members: Eric Fargnoli, Colby Weingarten
Drexel ECE Senior Design Award - Computer Engineering
Academic Year 2008-2009
- Design of and Addressable Internetworked Nanowire Sensor Platform (co-advised with Dr. Nabet)
Members: Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak
Fabricated a 1.5x1.5 mm chip in AMI 0.5um technology
Publication:
- K. Yencha, M. Zofchak, D. Oakum, G. Strait, B. Taskin, B. Nabet, "Design of an Addressable Internetworked Microscale Sensor", Special Issue: Journal of Selected Areas in Microelectronics (JSAM), December 2010.
Academic Year 2006-2007
- Automated Clock Signal Router for the 36GHz Processor
Members: Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner
Drexel ECE Senior Design Award - Computer Engineering
Publications:
- Baris Taskin, J. DeMaio, O. Farell, M. Hazeltine, R. Ketner, Custom Topology Rotary Clock Router, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 3, Article 44, May 2009.
- University Booth Presentation at the ACM/IEEE Design Automation Conference 2007 in San Diego, CA.
- Serial Memory Design Using QCA Nanoarchitectures
Members: Andy Chiu, Jonathan Salkind, Daniel Venutolo
Publications:
- Baris Taskin, A. Chiu, J. Salkind, D. Venutolo, A Shift-Register Based QCA Memory Architecture, ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009.
- Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Ventutolo, A Shift-Register Based QCA Memory Architecture, Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), October 2007, pp. 54--61.
- Realizing Arbitrary Boolean Functions with Analog Threshold Logic Circuits (co-advised with Dr. Katz)
Members: James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers
- Scalable Implementation of Graph Clustering Algorithm (co-advised with Dr. Hong)
Members: Mary Vuong, Ana Luiza Silva, Nemanja Milosavljevic, Jonathan Gevaryahu
Academic Year 2005-2006
- Automated Implementation of Logical Effort
Members: David Dimm, Roshani Patel
