Tutorials: Difference between revisions

From VLSILab
Jump to navigationJump to search
No edit summary
m (Add SynchroTrace tutorial links)
 
(9 intermediate revisions by 2 users not shown)
Line 1: Line 1:
== IISWC 2015 ==
== 2018 ==
=== October 4-6, Atlanta, Georgia, USA ===
=== IEEE International Green and Sustainable Computing Conference (IGSC) ===
'''October 22-24, Pittsburgh, Pennsylvania, USA'''


'''''Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation'''''
'''''Energy-Efficient and Secure Computing Systems ''''' (w/ Prof. Emre Salman, Stony Brook University)


----
== 2016 ==
=== IEEE International Symposium on Workload Characterization (IISWC) ===
'''September 25-27, Providence, Rhode Island, USA'''


[http://vlsi.ece.drexel.edu/index.php?title=Tutorials%3ASynchroTrace_Sigil_IISWC_2016 '''''Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation '''''] (w/ Prof. Mark Hempstead, Tufts University)


'''Topic Outline'''  
== 2015 ==
=== IEEE International Conference on Computer Design (ICCD) ===
'''October 18-21, New York City, New York, USA'''


Trace capture & analysis for multi-threaded programs, large design space exploration, and insights from workload profiling (e.g. accelerator design via hw/sw co-design and related architectural decisions).
[http://vlsi.ece.drexel.edu/index.php?title=Tutorials%3ASynchroTrace_Sigil_ICCD_2015 '''''Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation'''''] (w/ Prof. Mark Hempstead, Tufts University)


'''Synopsis'''


The [[SynchroTrace]] simulation framework enables exploration of a large design space. It has demonstrated speed and accuracy in aiding uncore designers for cache and network-on-chip design decisions, and is currently being integrated into Gem5 as an official patch.
=== IEEE International Symposium on Workload Characterization (IISWC) ===
'''October 4-6, Atlanta, Georgia, USA'''


[http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil] is our workload profiling toolset that has enabled SynchroTrace. It captures and classifies a workload's computation and communication operations, and intercepts synchronization actions within threads. Sigil has been used for accelerator co-design research by gathering communication edges between functions/threads to provide insight to the ''true'' cost of a workload. Additionally, its unique ability to create non-deterministic traces in a multithreaded trace is utilized for truly architecture-agnostic simulations.
[http://vlsi.ece.drexel.edu/index.php?title=Tutorials%3ASynchroTrace_Sigil_IISWC_2015 '''''Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation''''']  (w/ Prof. Mark Hempstead, Tufts University)


'''Agenda'''


In this talk we discuss the utility and impact of SynchroTrace and Sigil, and show examples downloading, building, and running the tools, along with analysis of the data produced.
=== IEEE International Symposium on Circuits and Systems (ISCAS) ===
'''May 24-27, Lisbon, Portugal'''
 
'''''Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances''''' (w/ Prof. Emre Salman, Stony Brook University)
 
 
== 2012 ==
=== ACM/IEEE International Conference on Computer-Aided Design (ICCAD) ===
'''November 5-8, San Jose, California, USA'''
 
'''''High Performance, Low Power Resonant Clocking''''' (w/ Prof. Matthew Guthaus, UCSC)

Latest revision as of 09:20, 12 August 2019

2018

IEEE International Green and Sustainable Computing Conference (IGSC)

October 22-24, Pittsburgh, Pennsylvania, USA

Energy-Efficient and Secure Computing Systems (w/ Prof. Emre Salman, Stony Brook University)

2016

IEEE International Symposium on Workload Characterization (IISWC)

September 25-27, Providence, Rhode Island, USA

Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation (w/ Prof. Mark Hempstead, Tufts University)

2015

IEEE International Conference on Computer Design (ICCD)

October 18-21, New York City, New York, USA

Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation (w/ Prof. Mark Hempstead, Tufts University)


IEEE International Symposium on Workload Characterization (IISWC)

October 4-6, Atlanta, Georgia, USA

Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation (w/ Prof. Mark Hempstead, Tufts University)


IEEE International Symposium on Circuits and Systems (ISCAS)

May 24-27, Lisbon, Portugal

Low Voltage Power Delivery and Clocking in Nanoscale Technologies: Basics to Recent Advances (w/ Prof. Emre Salman, Stony Brook University)


2012

ACM/IEEE International Conference on Computer-Aided Design (ICCAD)

November 5-8, San Jose, California, USA

High Performance, Low Power Resonant Clocking (w/ Prof. Matthew Guthaus, UCSC)

Retrieved from "https://research.coe.drexel.edu/ece/vlsi/index.php?title=Tutorials&oldid=4666"