Can Sitik: Difference between revisions
From VLSILab
Jump to navigationJump to search
No edit summary |
No edit summary |
||
| Line 9: | Line 9: | ||
==Research Interests== | ==Research Interests== | ||
* Electronic Design Automation(EDA) for | * Electronic Design Automation(EDA) for VLSI Design | ||
* Clock Tree/Mesh Synthesis | * Clock Tree/Mesh Synthesis | ||
* Clock Network | * Low-power Placement and Clock Network Design | ||
==Teaching== | ==Teaching== | ||
Revision as of 20:06, 12 November 2011
Education
Ph.D. in Computer Engineering, 2011 - Present
- Drexel University, Philadelphia, Pennsylvania, USA
B.S. in Electrical and Electronics Engineering, 2011
- Middle East Technical University(METU), Ankara, Turkey
Research Interests
- Electronic Design Automation(EDA) for VLSI Design
- Clock Tree/Mesh Synthesis
- Low-power Placement and Clock Network Design
Teaching
- Please refer to my Weekly Schedule for appointment
Contact Information
Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104
Email: as3577@drexel.edu
