Ying Teng: Difference between revisions

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== Selected Publications ==
== Selected Publications ==
# Y. Teng and B. Taskin, "Synchronization Scheme for Brick-based Rotary Oscillator Arrays", to appear in the ''Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI)", May 2012.
# Y. Teng and B. Taskin, "Synchronization Scheme for Brick-based Rotary Oscillator Arrays", to appear in the ''Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012.
# Y. Teng, J. Lu and B.Taskin, "ROA-brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', Oct. 2011, pp.273--278.
# Y. Teng, J. Lu and B.Taskin, "ROA-brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', Oct. 2011, pp.273--278.
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration Systems (TVLSI)''.
# Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration Systems (TVLSI)''.

Revision as of 16:29, 11 March 2012

Education

Ph.D. in Computer Engineering, 2009-Present

Drexel University, Philadelphia, Pennsylvania, USA

M.S. in Computer Engineering, 2007

Tianjin University, Tianjin, China

B.S. in Electrical and Computer Engineering, 2004

Tianjin University, Tianjin, China.

Research Interests

  • Resonant Adiabatic Clocking
  • Adiabatic Circuit Design
  • Physical Design in general including Floorplanning, Placement and Routing
  • Digital, Analog and Mixed Signal Integrated Circuits


Selected Publications

  1. Y. Teng and B. Taskin, "Synchronization Scheme for Brick-based Rotary Oscillator Arrays", to appear in the Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), May 2012.
  2. Y. Teng, J. Lu and B.Taskin, "ROA-brick Topology for Rotary Resonant Clocks", Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2011, pp.273--278.
  3. Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs", IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
  4. Y. Teng and B. Taskin, “Process Variation Sensitivity of the Rotary Traveling Wave Oscillator”, Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2011.
  5. Y. Teng and B. Taskin, “Look-up Table Based Low Power Rotary Travelling Wave Oscillator Design Considering the Skin Effect”, Journal of Low Power Electronics (JOLPE) [featured on the cover page].
  6. Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, "Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings", to appear in the Proceedings of the International Conference on VLSI Design (VLSID), January 2011.

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104

Phone: (302) 690-1775
Fax: (215) 895-1695
Email: yt74@drexel.edu