Vasil Pano: Difference between revisions
From VLSILab
Jump to navigationJump to search
| (68 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
[[File:vasil_pic.jpg| | [[File:vasil_pic.jpg|275px|thumb|right|[[Vasil Pano]]]] | ||
== Education == | == Education == | ||
:'''PhD in | :'''PhD in Electrical Engineering, 2019''' <br> | ||
::Drexel University, Philadelphia, PA. | ::Drexel University, Philadelphia, PA. | ||
:'''B.S. in Computer Engineering, 2014''' <br> | :'''B.S. in Computer Engineering, 2014''' <br> | ||
| Line 13: | Line 14: | ||
:* Communication Infrastructure | :* Communication Infrastructure | ||
==Curriculum Vitae== | ==Resume - Curriculum Vitae== | ||
:[[media:Vasil Pano Resume.pdf | Vasil Pano CV ( | :[[media:Vasil Pano Resume.pdf | Vasil Pano Resume CV (September 2024)]] | ||
== Publications == | == Publications == | ||
====Relevant Journal Publications==== | |||
#'''Vasil Pano''', Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", ''IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)'', March 2020. [http://vlsi.ece.drexel.edu/images/7/7c/VasilPano_JETCAS_Multi-Band.pdf PRE-PRINT] | |||
#Ankit More, '''Vasil Pano''', and Baris Taskin, "Vertical Arbitration-free 3D NoCs," ''IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)'', October 2017. [https://ieeexplore.ieee.org/document/8090893 PAPER] | |||
==== | ====Relevant Conference Publications==== | ||
# | #'''Vasil Pano''', Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", ''Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS)'', October 2019. [https://dl.acm.org/citation.cfm?id=3352380 PAPER] | ||
#'''Vasil Pano''', Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018. [https://ieeexplore.ieee.org/document/8351621 PAPER] | |||
#'''Vasil Pano''', Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753330 PAPER] | |||
#Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2018 | #'''Vasil Pano''', Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016. [https://ieeexplore.ieee.org/document/7753313 PAPER] | ||
# | |||
#Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2016 | |||
== Tutorial/Poster Presentations == | == Tutorial/Poster Presentations == | ||
# Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - '''Best Poster Award''' | |||
# Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016 | # Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at ''Design Automation Conference (DAC)'', 2016 | ||
# Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015. | # Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at ''IEEE International Conference on Computer Design (ICCD)'', 2015. | ||
| Line 35: | Line 35: | ||
== Teaching Assistant Coursework == | == Teaching Assistant Coursework == | ||
:; Academic Year 2018-2019 | |||
:: Digital Systems Projects (Spring 2018-19, ''Junior Level Class'') | |||
:: Internet Architecture and Protocols (Winter 2018-19, ''Graduate Level Class'') | |||
:: Digital Logic Design (Fall 2018-19, ''Sophomore Level Class'') | |||
:; Academic Year 2017-2018 | :; Academic Year 2017-2018 | ||
:: Design with Microcontrollers (Summer 2017-2018, ''Junior Level Class'') | |||
:: Digital Systems Projects (Spring 2017-2018, ''Junior Level Class'') | |||
:: Computation Lab II (Winter 2017-2018, ''Freshmen Level Class'') | |||
:: Parallel Computer Architecture (Winter 2017-2018, ''Graduate Level Class'') | |||
:: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'') | :: Digital Systems Projects (Fall 2017-2018, ''Junior Level Class'') | ||
:; Academic Year 2016-2017 | :; Academic Year 2016-2017 | ||
:: Systems Programming (Summer 2016-2017, ''Junior Level Class'') | |||
:: Digital Logic Design (Spring 2016-2017, ''Sophomore Level Class'') | |||
:: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'') | :: Parallel Computer Architecture (Winter 2016-2017, ''Graduate Level Class'') | ||
:; Academic Year 2015-2016 | :; Academic Year 2015-2016 | ||
:: High Performance Computer Architecture (Spring 2015-2016, ''Graduate Level Class'') | |||
:: Systems Programming (Winter 2015-2016, ''Junior Level Class'') | |||
:: Computation Lab II (Winter 2015-2016, ''Freshmen Level Class'') | |||
:: Computation Lab I (Fall 2015-2016, ''Freshmen Level Class'') | |||
:: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'') | :: Parallel Computer Architecture (Fall 2015-16, ''Graduate Level Class'') | ||
:; Academic Year 2014-2015 | :; Academic Year 2014-2015 | ||
:: Systems Programming (Summer 2014-15, ''Junior Level Class'') | |||
:: Digital Systems Projects (Spring 2014-15, ''Junior Level Class'') | |||
:: Internet Architecture and Protocols (Winter 2014-15, ''Junior Level Class'') | |||
:: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'') | :: Digital Logic Design (Fall 2014-15, ''Sophomore Level Class'') | ||
:; Academic Year 2013-2014 | :; Academic Year 2013-2014 | ||
:: ASIC Design II (Spring 2013-14, ''Graduate Level Class'') | |||
:: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'') | :: Network-on-chip I (Fall 2013-14, ''Graduate Level Class'') | ||
==Contact Information== | ==Contact Information== | ||
| Line 67: | Line 79: | ||
'''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] <br> | '''Email:''' [mailto:vasilpano@gmail.com vasilpano@gmail.com] <br> | ||
'''Linkedin:''' [https://www.linkedin.com/in/ | '''Linkedin:''' [https://www.linkedin.com/in/vasilpano Vasil Pano] | ||
Latest revision as of 10:53, 18 September 2024
Education
- PhD in Electrical Engineering, 2019
- Drexel University, Philadelphia, PA.
- B.S. in Computer Engineering, 2014
- Drexel University, Philadelphia, PA.
Research Interests
- Network on Chip
- Computer Architecture
- Memory Coherence Protocols
- Communication Infrastructure
Resume - Curriculum Vitae
Publications
Relevant Journal Publications
- Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), March 2020. PRE-PRINT
- Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), October 2017. PAPER
Relevant Conference Publications
- Vasil Pano, Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS), October 2019. PAPER
- Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018. PAPER
- Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016. PAPER
- Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016. PAPER
Tutorial/Poster Presentations
- Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - Best Poster Award
- Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at Design Automation Conference (DAC), 2016
- Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at IEEE International Conference on Computer Design (ICCD), 2015.
- Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at Mid-Atlantic (ASEE), 2014
Teaching Assistant Coursework
- Academic Year 2018-2019
- Digital Systems Projects (Spring 2018-19, Junior Level Class)
- Internet Architecture and Protocols (Winter 2018-19, Graduate Level Class)
- Digital Logic Design (Fall 2018-19, Sophomore Level Class)
- Academic Year 2017-2018
- Design with Microcontrollers (Summer 2017-2018, Junior Level Class)
- Digital Systems Projects (Spring 2017-2018, Junior Level Class)
- Computation Lab II (Winter 2017-2018, Freshmen Level Class)
- Parallel Computer Architecture (Winter 2017-2018, Graduate Level Class)
- Digital Systems Projects (Fall 2017-2018, Junior Level Class)
- Academic Year 2016-2017
- Systems Programming (Summer 2016-2017, Junior Level Class)
- Digital Logic Design (Spring 2016-2017, Sophomore Level Class)
- Parallel Computer Architecture (Winter 2016-2017, Graduate Level Class)
- Academic Year 2015-2016
- High Performance Computer Architecture (Spring 2015-2016, Graduate Level Class)
- Systems Programming (Winter 2015-2016, Junior Level Class)
- Computation Lab II (Winter 2015-2016, Freshmen Level Class)
- Computation Lab I (Fall 2015-2016, Freshmen Level Class)
- Parallel Computer Architecture (Fall 2015-16, Graduate Level Class)
- Academic Year 2014-2015
- Systems Programming (Summer 2014-15, Junior Level Class)
- Digital Systems Projects (Spring 2014-15, Junior Level Class)
- Internet Architecture and Protocols (Winter 2014-15, Junior Level Class)
- Digital Logic Design (Fall 2014-15, Sophomore Level Class)
- Academic Year 2013-2014
- ASIC Design II (Spring 2013-14, Graduate Level Class)
- Network-on-chip I (Fall 2013-14, Graduate Level Class)
Contact Information
Address:
3141 Chestnut Street
ECE Department, Bossone 405
Drexel University
Philadelphia
Pennsylvania 19104
Email: vasilpano@gmail.com
Linkedin: Vasil Pano
