Jianchao Lu: Difference between revisions
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==Curriculum Vitae== | ==Curriculum Vitae== | ||
[http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/ | [http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/5/51/Jlu_cv_v2.pdf CV (Nov 2010)] | ||
== Publications == | == Publications == | ||
Revision as of 10:13, 17 November 2010
Education
Ph.D. in Computer Engineering, 2007-Present
- Drexel University, Philadelphia, Pennsylvania, USA
M.S. in Computer Engineering, 2009
- Drexel University, Philadelphia, Pennsylvania, USA
B.S. in Electronics and Information Engineering, 2007
- Zhejiang University, Hangzhou, China.
Research Interests
- Clock Network Synthesis including Clock Tree/Mesh Synthesis and Resonant Clocking
- Physical Design in general including Floorplanning, Placement and Routing
- Clock Skew Scheduling
- Static and Statistical Timing analysis
- Parallel Computing
Curriculum Vitae
Publications
To see publications by the VLSI Lab at Drexel University please click here
Contact Information
Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104
Phone: (215) 301-8795
Fax: (215) 895-1695
Email: jl597@drexel.edu
