Publications

Books and Book Chapters

1. Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, Timing Optimization through Clock Skew Scheduling, Springer, 2009.
2. Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, System Timing, Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006

• 

  Springer link [1]

• 

  Amazon link [2]

Journals

1. Baris Taskin and I. S. Kourtev, Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit, International Journal on Circuits, Systems and Computers (JCSC), (in print)
2. Baris Taskin, J. DeMaio, O. Farell, M. Hazeltine, R. Ketner, Custom Topology Rotary Clock Router, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 3, Article 44, May 2009.
3. Baris Taskin, A. Chiu, J. Salkind, D. Venutolo, A Shift-Register Based QCA Memory Architecture, ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009.
4. Baris Taskin and Bo Hong, Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 12, pp. 1648--1656, December 2008.
5. Baris Taskin and Ivan S. Kourtev, Delay Insertion Method in Clock Skew Scheduling, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 4, pp. 651--663, April 2006.
6. Baris Taskin and Ivan S. Kourtev, Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 1, pp.~12--27, January 2004.