Can Sitik: Difference between revisions
From VLSILab
Jump to navigationJump to search
No edit summary |
No edit summary |
||
| Line 9: | Line 9: | ||
==Research Interests== | ==Research Interests== | ||
* Electronic Design Automation([http://en.wikipedia.org/wiki/Electronic_design_automation EDA] | * Electronic Design Automation(EDA) for Physical Design of VLSI Circuits, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?] | ||
* VLSI CAD for Timing and Power | * VLSI CAD for Timing and Power | ||
* Clock Tree/[http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html | * Clock Tree/Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits] | ||
* High Performance Clock Network Design | * High Performance Clock Network Design | ||
Revision as of 21:16, 30 August 2012
Education
Ph.D. in Computer Engineering, 2011 - Present
- Drexel University, Philadelphia, Pennsylvania, USA
B.S. in Electrical and Electronics Engineering, 2011
- Middle East Technical University(METU), Ankara, Turkey
Research Interests
- Electronic Design Automation(EDA) for Physical Design of VLSI Circuits, what is EDA?
- VLSI CAD for Timing and Power
- Clock Tree/Mesh Synthesis, clock mesh benefits
- High Performance Clock Network Design
Teaching
- ECE-E421: Advanced Electronics I (Fall 11-12)
- ECE-C304: Design with Microcontrollers (Winter, Summer 11-12)
- ENGR-231: Linear Engineering Systems (Spring 11-12)
- Please refer to my Weekly Schedule to ask for an appointment
Contact Information
Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104
Email: as3577@drexel.edu
