Can Sitik: Difference between revisions
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* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?] | * Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?] | ||
* Physical Design of System-on-Chips | * Physical Design of System-on-Chips | ||
==Publications== | |||
# Can Sitik and Baris Taskin, "Variation-Aware Multi-Voltage Domain Clock Mesh Design", to appear in the ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013. | |||
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", to appear in the ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013. | |||
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Group Conference Silicon Valley (SNUG)'', March 2013. | |||
# Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", to appear in the ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2013. | |||
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", in the ''Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)'', November 2012, pp. 691--697. | |||
# Can Sitik and Baris Taskin, [[media:ICCD_2012_Can.pdf|"Multi-Voltage Domain Clock Mesh Design"]], ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206. | |||
==Teaching== | ==Teaching== | ||
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* ECE-E421: Advanced Electronics I (Fall 2011) | * ECE-E421: Advanced Electronics I (Fall 2011) | ||
:Please refer to my [[Weekly Schedule]] to ask for an appointment | :Please refer to my [[Weekly Schedule]] to ask for an appointment | ||
==Contact Information== | ==Contact Information== | ||
'''Address:''' <br> | '''Address:''' <br> | ||
Revision as of 14:40, 17 February 2013
Education
Ph.D. in Computer Engineering, 2011 - Present
- Drexel University, Philadelphia, Pennsylvania, USA
B.S. in Electrical and Electronics Engineering, 2011
- Middle East Technical University(METU), Ankara, Turkey
Research Interests
- High-Performance/Low-Power Clock Networks
- Low Swing Clock Trees
- Clock Mesh Synthesis, clock mesh benefits
- Electronic Design Automation(EDA) for VLSI, what is EDA?
- Physical Design of System-on-Chips
Publications
- Can Sitik and Baris Taskin, "Variation-Aware Multi-Voltage Domain Clock Mesh Design", to appear in the Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013.
- Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", to appear in the Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013.
- Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", Proceedings of Synopsys User Group Conference Silicon Valley (SNUG), March 2013.
- Ying Teng and Baris Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", to appear in the Proceedings of the Design, Automation and Test in Europe (DATE), March 2013.
- Jianchao Lu, Xiaomi Mao and Baris Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", in the Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2012, pp. 691--697.
- Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 201--206.
Teaching
- ECE-C304: Design with Microcontrollers (Winter 2012-13, Summer 2012)
- ENGR-231: Linear Engineering Systems (Spring, Fall 2012)
- ECE-E421: Advanced Electronics I (Fall 2011)
- Please refer to my Weekly Schedule to ask for an appointment
Contact Information
Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104
Email: as3577@drexel.edu
Linkedin: A. Can Sitik
