Karthik Sangaiah: Difference between revisions

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<!--[[File:profilpic.png|right|border|frame|[[Can Sitik]]|25px]]-->
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<!--==Education==
==Education==
'''Ph.D. in Computer Engineering, 2013 - Present''' <br>  
'''Ph.D. in Computer Engineering, 2013 - Present''' <br>  
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania
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==Research Interests==
==Research Interests==
* High-Performance/Low-Power Clock Networks
* Computer Architecture
* Low Swing Clock Trees
* Digital Design
* Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]
* Embedded Systems Design
* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]
* Mixed-signal Embedded Systems
* Physical Design of System-on-Chips
* Physical Design of System-on-Chips


==Curriculum Vitae==
<!--==Curriculum Vitae==
[[media:Can_CV.pdf | Can Sitik CV (June 2013)]]
[[media:Can_CV.pdf | Can Sitik CV (June 2013)]]-->


==Publications==
==Publications==
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", to appear in the ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013.
# K. Sangaiah and P. Nagvajara, "Variable fractional digital delay filter on reconfigurable hardware," in Proceedings of IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, pages 430-433.
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.
# Nilakantan, S.; Annangi, S.; Gulati, N.; Sangaiah, K.; Hempstead, M., "Evaluation of an accelerator architecture for Speckle Reducing Anisotropic Diffusion," Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011 Proceedings of the 14th International Conference on, 9-14 Oct. 2011, pp.185-194.
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.
[http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&hl=en '''Google Scholar Page''']-->


==Teaching==
==Teaching==

Revision as of 15:48, 24 October 2013


Education

Ph.D. in Computer Engineering, 2013 - Present

Drexel University, Philadelphia, Pennsylvania

B.S. and M.S. in Computer Engineering, 2012

Drexel University, Philadelphia, Pennsylvania

Research Interests

  • Computer Architecture
  • Digital Design
  • Embedded Systems Design
  • Mixed-signal Embedded Systems
  • Physical Design of System-on-Chips


Publications

  1. K. Sangaiah and P. Nagvajara, "Variable fractional digital delay filter on reconfigurable hardware," in Proceedings of IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, pages 430-433.
  2. Nilakantan, S.; Annangi, S.; Gulati, N.; Sangaiah, K.; Hempstead, M., "Evaluation of an accelerator architecture for Speckle Reducing Anisotropic Diffusion," Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011 Proceedings of the 14th International Conference on, 9-14 Oct. 2011, pp.185-194.

Teaching


Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104

Email: ks499@drexel.edu

Linkedin: Karthik Sangaiah

Retrieved from "https://research.coe.drexel.edu/ece/vlsi/index.php?title=Karthik_Sangaiah&oldid=961"