Scott Lerner: Difference between revisions
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== Selected Publications == | == Selected Publications == | ||
# C. Sitik, S. Lerner, and B. Taskin, Low Swing Clock Tree Synthesis with Local Gate Clusters, Paper submitted to Design Automation | # C. Sitik, S. Lerner, and B. Taskin, Low Swing Clock Tree Synthesis with Local Gate Clusters, Paper submitted to Design Automation Conference (DAC), June 2015. | ||
# S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015. | # S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015. | ||
# C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014. | # C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014. | ||
Revision as of 09:32, 19 February 2015
Education
PhD in Electrical Engineering expected graduation 2018
- Drexel University, Philadelphia, PA.
B.S. in Electrical Engineering, 2014
- Drexel University, Philadelphia, PA.
B.S. in Computer Engineering, 2014
- Drexel University, Philadelphia, PA.
Research Interests
- Physical Design including Floorplanning, Placement and Routing
- Interconnect Modeling
- Low-swing Clock Tree Topologies
Curriculum Vitae
Selected Publications
- C. Sitik, S. Lerner, and B. Taskin, Low Swing Clock Tree Synthesis with Local Gate Clusters, Paper submitted to Design Automation Conference (DAC), June 2015.
- S. Nilakantan, S. Lerner, M. Hempstead and B. Taskin, Can you trust your memory trace?: A comparison of memory traces from binary instrumentation and simulation, Presented at the IEEE International Conference on VLSI Design (VLSIDESIGN), January 2015.
- C. Sitik, S. Lerner, and B. Taskin, Timing Characterization of Clock Buffers for Clock Tree Synthesis, Paper presented at ICCD, October 2014.
Poster Presentations
- S. Lerner, V. Pano, and B. Taskin, Wireless Network-on-Chip, Poster to be presented at Mid-Atlantic ASEE, November 2014
- S. Lerner, Arduino Robotics in the Classroom, Poster to be presented at Mid-Atlantic ASEE, November 2014
- Scott Lerner, and Baris Taskin, Low-Power Clock Network Designs, Poster presented at IEEE Design Automation Conference, June 2014
- S. Lerner, C. Sitik, and B. Taskin, Low Swing Clocking Algorithm for 20nm FinFET Technology, Poster presented at Upsilon Pi Epsilon Research Reception, February 2014.
- S. Lerner, C. Sitik, and B. Taskin, Sub-45nm Interconnect Modeling, Poster presented at Drexel IEEE Graduate Forum, February 2014.
- S. Lerner, R. Welliver, B. Derveni, C. Schoenfield, I. Yilmaz, MotionExplorer, A Leap Motion-Controlled Electric Wheelchair, presented at Philly Codefest, February 2014.
- C. Sitik, S. Lerner, and B. Taskin, Low-Power/High-Performance Clock Network Design for Microprocessors, Poster presented at Upsilon Pi Epsilon Research Reception, February 2013.
Awards
- NSF Research Experience for Undergraduate (REU) Grant 2014
- A. Richard Newton Young Fellow Award 2014
- Dean's Choice Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
- NextFab Innovation Award at Philly Codefest for MotionExplorer 2014 held in Philadelphia, PA
- Doctor Thomas Moore Endowed Grant 2014
- Dean's List, 2009, 2010, 2011, 2012, 2013, 2014
Selected Projects
- Leap Motion-Controlled Electric Wheelchair, Philly Codefest, February 2014
Contact Information
Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104
Phone: (863) 307-6194
Fax: (215) 895-1695
Email: spl29@drexel.edu
