Teaching

Courses

ECE-C 471 Introduction to VLSI Design

ECE-C 472 VLSI Design and Automation

ECE-C 472 Modern VLSI IC Design

ECE-C 671 EDA for VLSI Design I

ECE-C 672 EDA for VLSI Design II

ECE-C 673 Deep Sub-Micron (DSM) IC Design

Senior Design

Academic Year 2008-2009

• Design of and Addressable Internetworked Nanowire Sensor Platform (co-advised with Dr. Nabet)

Members: Daniel Oakum, Gerre Strait, Kyle Yencha, Matthew Zofchak

Fabricated a 1.5x1.5 mm2 chip in AMI 0.5um technology

Academic Year 2006-2007

• Automated Clock Signal Router for the 36GHz Processor

Members: Joseph DeMaio, Owen Farrell, Michael Hazeltine, Ryan Ketner

Drexel ECE Senior Design Award - Computer Engineering

Publications:

1. Baris Taskin, J. DeMaio, O. Farell, M. Hazeltine, R. Ketner, Custom Topology Rotary Clock Router, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 3, Article 44, May 2009.
2. University Booth Presentation at the ACM/IEEE Design Automation Conference 2007 in San Diego, CA.

• Serial Memory Design Using QCA Nanoarchitectures

Members: Andy Chiu, Jonathan Salkind, Daniel Venutolo

Publications:

1. Baris Taskin, A. Chiu, J. Salkind, D. Venutolo, A Shift-Register Based QCA Memory Architecture, ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009.
2. Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Ventutolo, A Shift-Register Based QCA Memory Architecture, Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), October 2007, pp. 54--61.

• Realizing Arbitrary Boolean Functions with Analog Threshold Logic Circuits (co-advised with Dr. Katz)

Members: James Cantwell, Matthew Kordbegli, Jason Myers, Scott Myers

• Scalable Implementation of Graph Clustering Algorithm (co-advised with Dr. Hong)

Members: Mary Vuong, Ana Luiza Silva, Nemanja Milosavljevic, Jonathan Gevaryahu

Academic Year 2005-2006

• Automated Implementation of Logical Effort

Members: