Vasil Pano

Vasil Pano

Education

PhD in Computer Engineering expected graduation 2018

Drexel University, Philadelphia, PA.

B.S. in Computer Engineering, 2014

Drexel University, Philadelphia, PA.

Research Interests

• Network on Chip
• Communication Infrastructure
• Computer Architecture

Curriculum Vitae

Vasil Pano CV (Feb 2016)

Publications

1. Vasil Pano, Isikcan Yilmaz and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," (to appear) Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016
2. Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," (to appear) Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016
3. Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication,” Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON), April 2015, pp. 1--6.

Tutorial/Poster Presentations

1. Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at Design Automation Conference (DAC), 2016
2. Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at IEEE International Conference on Computer Design (ICCD), 2015.
3. Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at Mid-Atlantic (ASEE), 2014

Teaching Assistant Coursework

High Performance Computer Architecture

Spring 2015-2016, Graduate Level Class

1. High Performance Computer Architecture, Spring 2015-2016, Graduate Level Class
2. Systems Programming, Winter 2015-2016, Junior Level Class
3. Computation Lab II, Winter 2015-2016, Freshmen Level Class
4. Computation Lab I, Fall 2015-2016, Freshmen Level Class
5. Introduction to Parallel Computer Architecture, Fall 2015-16, Graduate Level Class
6. Systems Programming, Summer 2014-15, Junior Level Class
7. Digital Systems Projects, Spring 2014-15, Junior Level Class
8. Internet Architecture and Protocols, Winter 2014-15, Junior Level Class
9. Digital Logic Design, Fall 2014-15, Sophomore Level Class
10. ASIC Design II, Spring 2013-14, Graduate Level Class
11. Network-on-chip I, Fall 2013-14, Graduate Level Class

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104

Phone: (215) 512-1519
Email: vasilpano@gmail.com