Software: Difference between revisions
From VLSILab
Jump to navigationJump to search
No edit summary |
No edit summary |
||
| Line 21: | Line 21: | ||
Implementing a slew-driven clock tree synthesis methodology. | Implementing a slew-driven clock tree synthesis methodology. | ||
| Line 28: | Line 26: | ||
A rotary resonant clock synthesizer in Cadence. | A rotary resonant clock synthesizer in Cadence. | ||
Latest revision as of 20:27, 8 February 2019
GitHUB page
Drexel VANDAL GitHub: https://github.com/VANDAL
SynchroTrace
SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.).
For details and download information see: SynchroTrace
Prism
Prism is a super-cool™ framework for easy analysis of applications. If you want to easily look at memory operations, function traces, IOPs/FLOPs, et al in an executed program, then check out Prism.
We have used it internally for workload-guided EDA tool flows, on-chip routing, thread-mapping, and in the design of architectural simulators.
SLECTS
Implementing a slew-driven clock tree synthesis methodology.
Rotary Resonant Clock Synthesizer
A rotary resonant clock synthesizer in Cadence.
