Jianchao Lu

Education

Ph.D. in Computer Engineering, 2011

Drexel University, Philadelphia, Pennsylvania, USA

B.S. in Electronics and Information Engineering, 2007

Zhejiang University, Hangzhou, China.

Research Interests

• Clock Network Synthesis including Clock Tree/Mesh Synthesis and Resonant Clocking
• Physical Design Methodologies in general including Floorplanning, Placement and Routing
• Power and Timing Optimization
• Static and Statistical Timing analysis
• Parallel Computing

Curriculum Vitae

Jianchao Lu CV (Jan 2011)

Journals

1. Jianchao Lu, Xiaomi Mao and Baris Taskin, "Integrated Clock Mesh Synthesis with Incremental Register Placement", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) (in pre-print)
2. Jianchao Lu, Ying Teng and Baris Taskin, "A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) (in pre-print).
3. Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment with Skew Tuning", ACM Transactions on Design Automation of Electronic Systems (TODAES) (in pre-print).
4. Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion", Journal of VLSI Design, Volume 2010 (2010), Article ID 451809.

Conferences

1. Ying Teng, Jianchao Lu and Baris Taskin, "ROA-Brick Topology for Rotary Resonant Clocks", to appear in the Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2011.
2. Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", Proceedings of the ACM International Symposium on Physical Design (ISPD), March 2011, pp. 131--138.
3. Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", Proceedings of the Design, Automation and Test in Europe (DATE), March 2011, pp. 455--460.
4. Jianchao Lu, Yusuf Aksehir and Baris Taskin, "Register On MEsh (ROME): A Novel Approach for Clock Mesh Network Synthesis", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2011.
5. Jianchao Lu and Baris Taskin, "Reconfigurable Clock Polarity Assignment for Peak Current Reduction of Clock-gated Circuits", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2011.
6. Jianchao Lu and Baris Taskin, "From RTL to GDSII: An ASIC Design Course Development using Synopsys University Program", Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2011.
7. Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, "Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings", Proceedings of the International Conference on VLSI Design (VLSID), January 2011.
8. Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010.
9. Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2010, pp. 765--770.
10. Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", Proceedings of the IEEE International SoC Design Conference (ISOCC), November 2009, pp.232--236.
11. Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 224--227.
12. Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 81--84.

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104

Phone: (215) 301-8795
Fax: (215) 895-1695
Email: jl597@drexel.edu