Can Sitik: Difference between revisions
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* Electronic Design Automation(EDA) for VLSI Design | * Electronic Design Automation(EDA) for VLSI Design | ||
* Clock Tree/Mesh Synthesis | * Clock Tree/Mesh Synthesis | ||
* Low-power | * Low-power Clock Network Design | ||
* Clock Network-Aware Placement | |||
==Teaching== | ==Teaching== | ||
Revision as of 23:43, 16 November 2011
Education
Ph.D. in Computer Engineering, 2011 - Present
- Drexel University, Philadelphia, Pennsylvania, USA
B.S. in Electrical and Electronics Engineering, 2011
- Middle East Technical University(METU), Ankara, Turkey
Research Interests
- Electronic Design Automation(EDA) for VLSI Design
- Clock Tree/Mesh Synthesis
- Low-power Clock Network Design
- Clock Network-Aware Placement
Teaching
- Please refer to my Weekly Schedule for appointment
Contact Information
Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104
Email: as3577@drexel.edu
