Jianchao Lu

Bio

Jianchao Lu received his B.S. in Electronic and Information Engineering from Zhejiang University in 2007. Currently he is working towards Ph.D. degree in the Electrical and Computer Engineering Department at Drexel University.

Research Interests

My research generally focus on the area of physical design and synthesis especially clock tree synthesis. I am also interested in the designing of parallel algorithms and their applications to VLSI design.

CV

Available soon.

Publications

1. Jianchao Lu and Baris Taskin, Incremental Register Placement for Low Power CTS, to appear in the IEEE International SoC Design Conference (ISOCC), Nov 2009
2. Jianchao Lu and Baris Taskin, Post-CTS Clock Skew Scheduling with Limited Delay Buffering, Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2009, pp. 224--227.
3. Baris Taskin and Jianchao Lu, Post-CTS Delay Insertion to Fix Timing Violations, Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 81--84.