Publications

Books and Book Chapters

1. Ivan S. Kourtev, Baris Taskin and Eby G. Friedman, Timing Optimization through Clock Skew Scheduling, Springer, 2009.
2. Baris Taskin, Ivan S. Kourtev and Eby G. Friedman, System Timing, Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006

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  Springer link [1]

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  Amazon link [2]

Journals

1. Baris Taskin and I. S. Kourtev, Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit, International Journal on Circuits, Systems and Computers (JCSC), (in print)
2. Baris Taskin, J. DeMaio, O. Farell, M. Hazeltine, R. Ketner, Custom Topology Rotary Clock Router, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 3, Article 44, May 2009.
3. Baris Taskin, A. Chiu, J. Salkind, D. Venutolo, A Shift-Register Based QCA Memory Architecture, ACM Journal on Emerging Technologies and Computation (JETC), Vol. 5, No. 1, Article 4, January 2009.
4. Baris Taskin and Bo Hong, Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 12, pp. 1648--1656, December 2008.
5. Baris Taskin and Ivan S. Kourtev, Delay Insertion Method in Clock Skew Scheduling, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 4, pp. 651--663, April 2006.
6. Baris Taskin and Ivan S. Kourtev, Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 1, pp.~12--27, January 2004.

Conferences

1. Vinayak Honkote and Baris Taskin, Zero Clock Skew Synchronization with Rotary Clocking Technology, Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2009, pp. 588--593.
2. Vinayak Honkote and Baris Taskin, Custom Rotary Clock Router, Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2008, pp. 114--119.
3. Baris Taskin and Jianchao Lu, Post-CTS Delay Insertion to Fix Timing Violations, Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 81--84.
4. Shannon Kurtas and Baris Taskin, Statistical Timing Analysis of Nonzero Clock Skew Circuits, Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 605--608 Best student paper award nominee.
5. Vinayak Honkote and Baris Taskin, Maze Router Based Scheme for Rotary Clock Router, Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS), August 2008, pp. 442--445.
6. Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Ventutolo, A Shift-Register Based QCA Memory Architecture, Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), October 2007, pp. 54--61.
7. Prawat Nagvajara and Baris Taskin, Design-for-Debug: A Vital Aspect in Education, Proceedings of the International Conference on Microelectronic Systems Education (MSE), June 2007, pp. 65--66.
8. Baris Taskin and Ivan S. Kourtev, A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2006, pp.~486--490.
9. Baris Taskin, John Wood and Ivan S. Kourtev, Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), August 2006, pp. 261--265.
10. Baris Taskin and Bo Hong, Dual-Phase Line-Based QCA Memory Design, Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO), July 2006, pp. 302--305.
11. Baris Taskin and Ivan S. Kourtev, Delay Insertion in Clock Skew Scheduling, Proceedings of the ACM International Symposium on Physical Design (ISPD), San Francisco, CA, Apr. 2005, pp. 47--54.
12. Baris Taskin and Ivan S. Kourtev, Performance Improvement of Edge-Triggered Sequential Circuits, Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2004, pp. 607--610.
13. Baris Taskin and Ivan S. Kourtev, Advanced Timing of Level-Sensitive Sequential Circuits, Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2004, pp. 603--606.
14. Baris Taskin and Ivan S. Kourtev, Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2004, Vol. 2, pp. II-617--620.
15. Baris Taskin and Ivan S. Kourtev, Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew, Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December 2002, pp. 111--117.
16. Baris Taskin and Ivan S. Kourtev, Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches, Proceedings of the 15th Annual IEEE International ASIC/SOC Conference, September 2002, pp.~358--362.