Research

Resonant Clocking Technologies

Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.

With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of this project are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.

Clock Skew Scheduling

Integrated circuits design at the sub-micron levels, particularly in the transition to 60 and lower technologies, requires paradigm shifts. In order to acheive high-performance, robust and high-yield production, design and manufacturing techniques are being investigated more carefully. A successful design at a sub-60nm technology can be achieved through employing a combination of design principles. Investigation and improvement of each design princliple is important and a contributing factor to prolonging the success of Moore's Law in CMOS based IC design.

In this research, an additional design principle---clock skew scheduling---to aid the design of deep sub-micron IC design is investigated. The performance enhancing effects of clock skew scheduling has been known for over 20 years. Designers employ ad hoc tricks to delay clock signals on timing violated paths to satisfy design budgets. Due to the scalability of the conventional application techniques, however, clock skew shceduling typically cannot be used to its full advantage. The common advantages of skew scheduling are known to be fixing timing violations and improving operating frequencies of circuits. In deep sub-micron design era, skew scheduling can effectively be used to imrove timing yield and enable low power design alternatives as well. Provided that the increasing computing power of multi-core systems can be applied to remedy the scalability problem and by reformulating the objectives, clock skew scheduling can be used as an additional design principle to enable high-yield IC design at 45nm and lower technologies.

Wireless On-Chip Interconnects

Increasing functionality and complexity in design of integrated circuits (ICs) requires careful planning for on-chip resources such as area and power. Critical design decisions are often given based on the availability of these resources within increasingly stringent design budgets. Among these typical IC design budgets, wire interconnects are one of the most expensive items. Significantly impacting the timing, power and area resources, wire interconnects constitute the complex infrastructure to establish communication and synchronization within a conventional, state-of-the-art IC.

In this project, wireless communication principles are investigated in order to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. By implementing one or many transmitter and receiver antennas on the same chip, wireless communication principles will be used to communicate between distant components within a chip. The proposed on-chip wireless communication implementations bear a constant overhead in area and power budgets in order to implement the antennas and surrounding circuitry. However, the increasing size and complexity of conventional wire interconnects (particularly for heavy-duty global interconnects such as clock and power lines) are mitigated, solving one of the major problems in state-of-the-art IC design process. Wireless communication will provide a solution that is highlyscalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.