Vasil Pano

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Vasil Pano


Education

PhD in Electrical Engineering, 2019
Drexel University, Philadelphia, PA.
B.S. in Computer Engineering, 2014
Drexel University, Philadelphia, PA.

Research Interests

  • Network on Chip
  • Computer Architecture
  • Memory Coherence Protocols
  • Communication Infrastructure

Resume - Curriculum Vitae

Vasil Pano Resume CV (March 2020)

Publications

Journal Publications

  1. Ragh Kuttappa, Baris Taskin, Scott Lerner, and Vasil Pano, "Resonant Clock Synchronization with Active Silicon Interposer for Multi-Die Systems", IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), Accepted February 2021.
  2. Vasil Pano, Ibrahim Tekin, Isikcan Yilmaz, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV Antennas for Multi-Band Wireless Communication", IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), March 2020. PRE-PRINT
  3. Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "TSV-based Antenna for On-Chip Wireless Communication", IET Microwaves, Antennas & Propagation (MAP), December 2019. PRE-PRINT
  4. Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, and Hamid Mahmoodi, "RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), January 2019. PAPER
  5. Ankit More, Vasil Pano, and Baris Taskin, "Vertical Arbitration-free 3D NoCs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), October 2017. PAPER

Conference Publications

  1. Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, and Baris Taskin, "Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2020. PAPER
  2. Vasil Pano, Ragh Kuttappa, Baris Taskin, "3D NoCs with Active Interposer for Multi-Die Systems", Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip (NOCS), October 2019. PAPER
  3. Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, and Ioannis Savidis, "Robust Low Power Clock Synchronization for Multi-Die Systems", Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2019. PAPER
  4. Vasil Pano, Ibrahim Tekin, Yuqiao Liu, Kapil R. Dandekar, and Baris Taskin, "In-Package Wireless Communication with TSV-based Antenna", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2019. PAPER
  5. Vasil Pano, Scott Lerner, Isikcan Yilmaz, Michael Lui, and Baris Taskin, "Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018. PAPER
  6. Scott Lerner, Vasil Pano, and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2018. PAPER
  7. Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2017. PAPER
  8. Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016. PAPER
  9. Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016. PAPER
  10. Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON), April 2015. PAPER

Tutorial/Poster Presentations

  1. Scott Lerner, Vasil Pano and Baris Taskin, "NoC Router Lifetime Improvement Using Per-Port Router Utilization," Poster presented at 10th Annual Drexel IEEE Graduate Symposium, April 2018 - Best Poster Award
  2. Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at Design Automation Conference (DAC), 2016
  3. Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at IEEE International Conference on Computer Design (ICCD), 2015.
  4. Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at Mid-Atlantic (ASEE), 2014

Teaching Assistant Coursework

Academic Year 2018-2019
Digital Systems Projects (Spring 2018-19, Junior Level Class)
Internet Architecture and Protocols (Winter 2018-19, Graduate Level Class)
Digital Logic Design (Fall 2018-19, Sophomore Level Class)
Academic Year 2017-2018
Design with Microcontrollers (Summer 2017-2018, Junior Level Class)
Digital Systems Projects (Spring 2017-2018, Junior Level Class)
Computation Lab II (Winter 2017-2018, Freshmen Level Class)
Parallel Computer Architecture (Winter 2017-2018, Graduate Level Class)
Digital Systems Projects (Fall 2017-2018, Junior Level Class)
Academic Year 2016-2017
Systems Programming (Summer 2016-2017, Junior Level Class)
Digital Logic Design (Spring 2016-2017, Sophomore Level Class)
Parallel Computer Architecture (Winter 2016-2017, Graduate Level Class)
Academic Year 2015-2016
High Performance Computer Architecture (Spring 2015-2016, Graduate Level Class)
Systems Programming (Winter 2015-2016, Junior Level Class)
Computation Lab II (Winter 2015-2016, Freshmen Level Class)
Computation Lab I (Fall 2015-2016, Freshmen Level Class)
Parallel Computer Architecture (Fall 2015-16, Graduate Level Class)
Academic Year 2014-2015
Systems Programming (Summer 2014-15, Junior Level Class)
Digital Systems Projects (Spring 2014-15, Junior Level Class)
Internet Architecture and Protocols (Winter 2014-15, Junior Level Class)
Digital Logic Design (Fall 2014-15, Sophomore Level Class)
Academic Year 2013-2014
ASIC Design II (Spring 2013-14, Graduate Level Class)
Network-on-chip I (Fall 2013-14, Graduate Level Class)

Contact Information

Address:
3141 Chestnut Street
ECE Department, Bossone 405
Drexel University
Philadelphia
Pennsylvania 19104

Email: vasilpano@gmail.com

Linkedin: Vasil Pano

Retrieved from "https://research.coe.drexel.edu/ece/vlsi/index.php?title=Vasil_Pano&oldid=5581"