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== M.S. Students ==
== M.S. Students ==
Kevin Daly
[[Sharat C. Shekar]]
Xiaomi Mao


John Vargas
John Vargas
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[[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: '' High Performance IC Clock Network Design with Mesh and Tree Topologies''
[[Jianchao Lu]] (Ph.D., 2011), [First job: Synopsys], Dissertation: '' High Performance IC Clock Network Design with Mesh and Tree Topologies''
Kevin Daly (MS, 2011) [First job: Washington, DC]
[[Sharat C. Shekar]] (MS, 2011) [First job: Samsung]
Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]


[[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''
[[Vinayak Honkote]] (Ph.D., 2010), [First job: Intel], Dissertation: ''Design Automation and Analysis of Resonant Clocking Technologies''

Revision as of 21:19, 2 June 2011

Faculty

Baris Taskin

Ph.D. Students

Ankit More

Ying Teng

M.S. Students

John Vargas

Undergraduate Researchers

Yusuf Aksehir (2010) [Sabanci University]

Abdalla Musmar (2010) [An-Najah National University]

Michael Edoror (2010) [University of Maryland]

Bo Hyun Kim (2010) [Carnegie Mellon University, graduate school at Columbia University]

S. Kutal Gokce (2008) [Middle East Technical University (METU), M.S. at Koc University, Ph.D. at UT-Austin]

Can Hankendi (2008) [Sabanci University, M.S. at USC, Ph.D. at Boston University]

Danh Nguyen (2007) [graduate school at Drexel University]

High-School Researchers

Ilteris K. Canberk (2010) [Robert College]

Group Alumni

Jianchao Lu (Ph.D., 2011), [First job: Synopsys], Dissertation: High Performance IC Clock Network Design with Mesh and Tree Topologies

Kevin Daly (MS, 2011) [First job: Washington, DC]

Sharat C. Shekar (MS, 2011) [First job: Samsung]

Xiaomi Mao (M.S., 2011) [First job: Oracle/Sun]

Vinayak Honkote (Ph.D., 2010), [First job: Intel], Dissertation: Design Automation and Analysis of Resonant Clocking Technologies

Yaswanth Simhadri (MS, 2008)

Shannon M. Kurtas (BS/MS, 2007) [First job: Intel], Thesis: Statistical Static Timing Analysis of Nonzero Clock Skew Circuits