Research: Difference between revisions
(Created page with '== Resonant Clocking Technologies == == Clock Skew Scheduling == == Low-Power Clock Tree Synthesis == == Quantum-Dot Cellular Automata (QCA) based Nanoarchitectures == == Wir...') |
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== Resonant Clocking Technologies == | == Resonant Clocking Technologies == | ||
Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production. | |||
With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of the proposed research are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers. | |||
== Clock Skew Scheduling == | == Clock Skew Scheduling == | ||
Revision as of 19:25, 13 June 2009
Resonant Clocking Technologies
Achieving high quality synchronization with low power dissipation is a major objective in synchronous VLSI circuit design at high frequency regimes. In order to meet this objective, conventional clock design methodologies are constantly being improved. Also, next-generation alternatives to conventional clocking have been emerging. Resonant clocking technologies provide operating frequencies and power dissipation levels that are unprecedented in the state-of-the-art, bulk-CMOS VLSI IC implementations. These technologies must be characterized for on chip variations, have robust simulation models and be supported by specific design flows in order to be viable in high volume production. This project addresses such challenges in the design and design automation of resonant clocking technologies for high-volume IC production.
With improved nanoscale design characterization and design automation methodologies, resonant clocking technologies can be seamlessly integrated within the mainstream VLSI IC design flow. The broader impacts of the proposed research are in revolutionizing the clock synchronization methodology of digital VLSI synchronous circuits for low-power, multi-GHz operation and providing its sustainability over semiconductor technology scaling. Proposed low-power, multi-GHz high-performance clocking operation will have a major impact on all microelectronic systems, from field-deployable low power sensors to the world's fastest supercomputers.
