Software: Difference between revisions
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== | == GitHUB page == | ||
Drexel VANDAL GitHub: https://github.com/VANDAL | |||
[ | |||
== SynchroTrace == | |||
[https://github.com/VANDAL/SynchroTrace-gem5 git.io/synchrotrace] | |||
SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.). | SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.). | ||
For details and download information see: [[SynchroTrace]] | |||
== Prism == | |||
[https://github.com/VANDAL/prism git.io/prism] | |||
Prism is a super-cool™ framework for easy analysis of applications. | |||
If you want to easily look at memory operations, function traces, IOPs/FLOPs, et al in an executed program, then check out Prism. | |||
We have used it internally for workload-guided EDA tool flows, on-chip routing, thread-mapping, and in the design of architectural simulators. | |||
== SLECTS == | == SLECTS == | ||
Implementing a slew-driven clock tree synthesis methodology. | Implementing a slew-driven clock tree synthesis methodology. | ||
| Line 13: | Line 24: | ||
== Rotary Resonant Clock Synthesizer== | == Rotary Resonant Clock Synthesizer== | ||
A rotary resonant clock synthesizer in Cadence. | A rotary resonant clock synthesizer in Cadence. | ||
Latest revision as of 21:27, 8 February 2019
GitHUB page
Drexel VANDAL GitHub: https://github.com/VANDAL
SynchroTrace
SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.).
For details and download information see: SynchroTrace
Prism
Prism is a super-cool™ framework for easy analysis of applications. If you want to easily look at memory operations, function traces, IOPs/FLOPs, et al in an executed program, then check out Prism.
We have used it internally for workload-guided EDA tool flows, on-chip routing, thread-mapping, and in the design of architectural simulators.
SLECTS
Implementing a slew-driven clock tree synthesis methodology.
Rotary Resonant Clock Synthesizer
A rotary resonant clock synthesizer in Cadence.
