Vinayak Honkote: Difference between revisions
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* Near Threshold Supply Voltage (NTV) Circuits | * Near Threshold Supply Voltage (NTV) Circuits | ||
* Large-Scale Optimization including LP and ILP | * Large-Scale Optimization including LP and ILP | ||
* Nanoscale Design, | * Emerging Technologies, Nanoscale Design, 3-D ICs | ||
* Post-CMOS Interconnects | * Post-CMOS Interconnects | ||
* Statistical Timing | * Statistical Timing | ||
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==Contact Information== | ==Contact Information== | ||
'''Address:''' <br> | |||
Intel Corporation <br> | |||
SoC Design Lab, Intel Labs <br> | |||
SRR2, Outer Ring Road, Varthur Hobli <br> | |||
Bangalore, Karnataka 560103 <br> | |||
INDIA <br> | |||
'''Phone:''' +919986041288 <br> | '''Phone:''' +919986041288 <br> | ||
'''Email:''' [[File:vinayak_email_image.png|125px|link=Email]] | '''Email:''' [[File:vinayak_email_image.png|125px|link=Email]] | ||
Revision as of 00:46, 12 January 2013
Education
Ph.D. in Electrical Engineering, 2010
- Drexel University, Philadelphia, Pennsylvania, USA
M.S. in Electrical Engineering, 2006
- Drexel University, Philadelphia, Pennsylvania, USA
B.E. in Electronics and Communications Engineering, 2003
- Bangalore Institute of Technology, Karnataka, India
Research Interests
- Cyber-Physical Systems (CPS), Display Technologies
- Human Computer Interaction (HCI), Computer Vision
- System-on-Chip (SOC) Design, Portable Electronic Devices
- Low Power VLSI Circuits, Adiabatic Circuits
- Clocking for SoCs and Multicore Systems, Resonant Clocking Technologies
- Near Threshold Supply Voltage (NTV) Circuits
- Large-Scale Optimization including LP and ILP
- Emerging Technologies, Nanoscale Design, 3-D ICs
- Post-CMOS Interconnects
- Statistical Timing
Curriculum Vitae
Publications
To see publications by the VLSI Lab at Drexel University please click here
Contact Information
Address:
Intel Corporation
SoC Design Lab, Intel Labs
SRR2, Outer Ring Road, Varthur Hobli
Bangalore, Karnataka 560103
INDIA
Phone: +919986041288
Email: 
