Ying Teng: Difference between revisions

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(Created page with '==Education== '''Ph.D. in Computer Engineering, 2009-Present''' <br> :Drexel University, Philadelphia, Pennsylvania, USA '''M.S. in Computer Engineering, 2007 ''' <br> :Tianji...')
 
 
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==Education==  
==Education==  
'''Ph.D. in Computer Engineering, 2009-Present''' <br>  
'''Ph.D. in Computer Engineering, 2009-2014''' <br>  
:Drexel University, Philadelphia, Pennsylvania, USA
:Drexel University, Philadelphia, Pennsylvania, USA


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==Research Interests==
==Research Interests==
* Clock Network Synthesis including Clock Tree/Mesh Synthesis and Resonant Clocking
* Resonant Adiabatic Clocking
* Adiabatic Circuit Design
* Physical Design in general including Floorplanning, Placement and Routing
* Physical Design in general including Floorplanning, Placement and Routing
* Clock Skew Optimization
* Digital, Analog and Mixed Signal Integrated Circuits
* Static and Statistical Timing analysis
 
* Parallel Computing


==Curriculum Vitae==
==Curriculum Vitae==
[http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/images/5/51/Jlu_cv_v2.pdf CV (Nov 2010)]
[[media:Ying_CV.pdf | Ying Teng CV (Feb 2014)]]
 


== Selected Publications ==
== Selected Publications ==
# Jianchao Lu, Xiaomi Mao and Baris Taskin, "Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis", to appear in the ''Proceedings of the ACM International Symposium on Physical Design (ISPD)'', March 2011.
# Y. Teng and B. Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", to appear in the ''Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013.
# Jianchao Lu, Vinayak Honkote, Xin Chen and Baris Taskin, "Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing", to appear in the ''Proceedings of the Design, Automation and Test in Europe (DATE)'', March 2011.
# Y. Teng and B. Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", to appear in the ''Proceedings of IEEE Design Automation and Test in Europe (DATE)'', March 2013.
# Vinayak Honkote, Ankit More, Ying Teng, Jianchao Lu and Baris Taskin, "Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings", to appear in the ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.
# Y. Teng and B. Taskin, "Clock Mesh Synthesis Method using the Earth Mover’s Distance under Transformations", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', Oct. 2012, pp.121--126.
# Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2010.
# Y. Teng and B. Taskin, "Synchronization Scheme for Brick-based Rotary Oscillator Arrays", ''Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI)'', May 2012.
# Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load", ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2010, pp. 765--770.
# Y. Teng, J. Lu and B. Taskin, "ROA-brick Topology for Rotary Resonant Clocks", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', Oct. 2011, pp.273--278.
# Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS", ''Proceedings of the IEEE International SoC Design Conference (ISOCC)'', November 2009, pp.232--236.
# J. Lu, Y. Teng and B. Taskin, "A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs", ''IEEE Transactions on Very Large Scale Integration Systems (TVLSI)''.
# Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2009, pp. 224--227.
# Y. Teng and B. Taskin, “Process Variation Sensitivity of the Rotary Traveling Wave Oscillator”, ''Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)'', March 2011.
# Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations", ''Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)'', August 2008, pp. 81--84.
# Y. Teng and B. Taskin, “Look-up Table Based Low Power Rotary Travelling Wave Oscillator Design Considering the Skin Effect”, ''Journal of Low Power Electronics (JOLPE)'' [featured on the cover page].
# V. Honkote, A. More, Y. Teng, J. Lu and B. Taskin, "Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings", to appear in the ''Proceedings of the International Conference on VLSI Design (VLSID)'', January 2011.  


==Contact Information==
==Contact Information==
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Pennsylvania 19104 <br>
Pennsylvania 19104 <br>


'''Phone:''' (215) 301-8795 <br>
'''Phone:''' (302) 690-1775 <br>
'''Fax:''' (215) 895-1695 <br>
'''Fax:''' (215) 895-1695 <br>
'''Email: '''jl597@drexel.edu
'''Email: '''yt74@drexel.edu

Latest revision as of 23:21, 18 December 2015

Education

Ph.D. in Computer Engineering, 2009-2014

Drexel University, Philadelphia, Pennsylvania, USA

M.S. in Computer Engineering, 2007

Tianjin University, Tianjin, China

B.S. in Electrical and Computer Engineering, 2004

Tianjin University, Tianjin, China.

Research Interests

  • Resonant Adiabatic Clocking
  • Adiabatic Circuit Design
  • Physical Design in general including Floorplanning, Placement and Routing
  • Digital, Analog and Mixed Signal Integrated Circuits


Curriculum Vitae

Ying Teng CV (Feb 2014)


Selected Publications

  1. Y. Teng and B. Taskin, "Rotary Traveling Wave Oscillator Frequency Division at Nanoscale Technologies", to appear in the Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), May 2013.
  2. Y. Teng and B. Taskin, "Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction", to appear in the Proceedings of IEEE Design Automation and Test in Europe (DATE), March 2013.
  3. Y. Teng and B. Taskin, "Clock Mesh Synthesis Method using the Earth Mover’s Distance under Transformations", Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2012, pp.121--126.
  4. Y. Teng and B. Taskin, "Synchronization Scheme for Brick-based Rotary Oscillator Arrays", Proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), May 2012.
  5. Y. Teng, J. Lu and B. Taskin, "ROA-brick Topology for Rotary Resonant Clocks", Proceedings of the IEEE International Conference on Computer Design (ICCD), Oct. 2011, pp.273--278.
  6. J. Lu, Y. Teng and B. Taskin, "A Reconfigur​able Clock Polarity Assignment Flow for Clock Gated Designs", IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
  7. Y. Teng and B. Taskin, “Process Variation Sensitivity of the Rotary Traveling Wave Oscillator”, Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2011.
  8. Y. Teng and B. Taskin, “Look-up Table Based Low Power Rotary Travelling Wave Oscillator Design Considering the Skin Effect”, Journal of Low Power Electronics (JOLPE) [featured on the cover page].
  9. V. Honkote, A. More, Y. Teng, J. Lu and B. Taskin, "Interconnect Modeling, Synchronization and Power Analysis for Custom Rotary Rings", to appear in the Proceedings of the International Conference on VLSI Design (VLSID), January 2011.

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia
Pennsylvania 19104

Phone: (302) 690-1775
Fax: (215) 895-1695
Email: yt74@drexel.edu

Retrieved from "https://research.coe.drexel.edu/ece/vlsi/index.php?title=Ying_Teng&oldid=1375"