Category: News

The papers entitled Increasing the SAT Attack Resiliency of In-Cone Logic Locking and Mesh Based Obfuscation of Analog Circuit Properties were presented at ISCAS 2019.

The Joseph and Shirley Carleone Endowed Fellowship for the academic year 2017-2018 is awarded to Divy Pathak by the College of Engineering, Drexel University.

Prof. Ioannis Savidis presented two ICE Lab papers at the Government Microcircuit Applications & Critical Technology Conference in Miami, Florida held on March 12-14, 2018:
1) Kyle Juretus and Ioannis Savidis, “Enhanced Circuit Security Through Hidden State Transitions.”
Abstract: A technique is developed that uses the state space of an integrated circuit (IC) to increase security. Timing path dependencies and coupling capacitance are utilized to create hidden state transitions that are not observable after netlist extraction. Temporal based transitions are also introduced to shift key dependencies into the time domain. The state space dependencies of the IC serve as a means to counter the SAT attack. Implementing temporal based transitions increases the area of the circuit by 68.42%, the power by 43.17%, and does not impact circuit delay. However, an increased circuit size significantly reduces the overhead of implementing state space encryption. For example, encrypting two registers in the s15850 ISCAS89 benchmark circuit resulted in an area overhead of 0.026%, providing a means to secure sequential logic with minimal overhead.

2) Vaibhav Venugopal Rao and Ioannis Savidis, “Dynamic Current Mode Inverter for Ultra-Low Power Near-Threshold Computing.”
Abstract: A technique to enhance the security of analog circuits using Satisfiability Modulo Theory (SMT) based design space exploration is described. The analog satisfiability (aSAT) technique takes as inputs generic circuit equations and performance constraints and, by exhaustively exploring the design space, outputs transistor sizes that satisfy the given constraints. The aSAT methodology is applied to parameter biasing obfuscation, where the width and length of a transistor are obfuscated to mask circuit properties. The proposed methodology was used in the design of a differential amplifier and an operational amplifier, where the widths and lengths determined through aSAT analysis were shown to meet the target circuit specifications. For the operational amplifier, transistor dimensions determined through aSAT analysis for a set of performance constraints were characterized and were found to meet the performance targets, however, there was a 7 MHz reduction in the gain bandwidth product. e simulated results indicate that the developed design methodology achieves a fast and accurate determination of transistor sizes for target specications.

The patent “Power supply voltage detection and power delivery circuit” is issued by the USPTO on March 6, 2018 as United States Patent Number 9,912,325. Prof. Ioannis Savidis and Divy Pathak are the co-founders of the patent.

The 2017 IEEE CASS Pre-Doctoral Scholarship is awarded to Divy Pathak.  She received the award at the 2017 IEEE ISCAS conference on May 31, 2017 at Baltimore, MD.

The Allen Rothwarf Scholarship for the academic year 2016-2017 is awarded to Divy Pathak by the Department of Electrical and Computer Engineering, Drexel University.

Divy Pathak is awarded the 2017 National Science Foundation Professional Development Award to participate in the iREDEFINE project.

Kyle Juretus presented “Reduced Overhead Gate Level Logic Encryption” and Prof. Ioannis Savidis presented “Load Balanced On-Chip Power Delivery for Average Current Demand” at the 2016 Great Lakes Symposium on Very Large Scale Integration (GLSVLSI).