Sub/Near-Threshold Circuits with Current-Mode Logic

Since power and energy have not scaled similarly to the dimension of the transistor, it has become difficult to operate all transistors simultaneously for a given power budget and time (concept of Dark silicon). In addition, the energy/power efficiency of mobile devices is critical to extend usage. One potential solution is to operate circuits in the sub-threshold or near-threshold regime. A reduction in supply voltage reduces dynamic power quadratically and static power exponentially. However, in the sub-threshold regime, performance degradation, reliability issues, and high leakage power severely affect the overall energy and power improvements. On the other hand, near-threshold devices are more tolerant to performance degradation and are more reliable. In addition, near-threshold circuits (NTC) are not as energy inefficient as sub-threshold circuits.

Current-mode logic (CML) circuits are well known for a higher operating speed as compared to conventional CMOS with a static leakage overhead. On the other hand, dynamic current-mode logic circuits (DCML) have reduced static leakage and are faster. Hence, DCML circuits are superior to CML in terms of power consumption and delay.

Power Reduction using NTC with CML (Current)

Our primary objective is to design circuits with minimum power consumption and higher energy efficiency. We implement NTC to minimize the power of the circuits. However, using purely near-threshold devices limits the maximum operating frequency and reduces the total system throughput. We address this issue by introducing DCML to NTC. In this fashion, we can trade-off between power and performance. In addition, the reduced voltages strain the design of these circuits. We are examining resilient circuit design and methodologies for NTCs with DCML.