Dr. Divy Pathak

Divy Pathak

Dr. Divy Pathak received the M.S. degree in Computer Engineering in 2015 and Ph.D. in Electrical Engineering in 2018 from Drexel University. She is the recipient of the 2017 IEEE Circuits and Systems Pre-Doctoral Scholarship. Dr. Pathak is the co-inventor in  two US Patents and four patent applications.

She was a Research Scientist with Indian Space Research Organization from 2003 to 2006, where she was involved in analog signal processing modules for communication and remote sensing satellites. She was a Staff Engineer with STMicroelectronics from 2006 to 2013, where she focused on functional and electrical post-silicon validation of set-top box MPSoCs. She was an Intern with the IBM Thomas J. Watson Research Center from 2015 to 2016, where she was involved in power supply noise mitigation techniques for IBM POWER and Z Systems.

Her current research interests include circuits, systems, and micro-architecture design for post-Moore computing, including algorithms, modeling, optimization, and VLSI design for computing devices ranging from exascale systems to low-power internet of things. Her Ph.D. thesis focuses on SMART on-chip power delivery for energy efficient computing.

Publications

Dissertation

D. Pathak, “SMART Grid On Chip: Infusing intelligence to on-chip energy management“, Ph.D. Thesis, Drexel University, December 2018.

Journal Publications

[J4] D. Pathak and I. Savidis, “On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors,”  IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 26, no. 11, pp. 2230-2240, November 2018.
[J3] M. Tavana, M. Hajkazemi, D. Pathak, I. Savidis, and H. Homayoun, “ElasticCore: A Dynamic Heterogeneous Platform with Joint Core and Voltage/Frequency Scaling,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 26, no. 2, pp. 249-261, February 2018.
[J2] D. Pathak, H. Homayoun, and I. Savidis, “SMART GRID ON CHIP: Load Balanced On-Chip Power Delivery,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 25, no. 9, pp. 2538-2551, September 2017.
[J1] V. Sinha, D. Pathak, A. Kumar, and O.P. Kaushik, “Survey of SAW Devices in Space,” International Journal of Space Craft technology, Vol. 18, no. 2, pp. 61-75, July 2008.

Conference Publications

[C14] D. Pathak and I. Savidis. “Applying Swarm Intelligence to Distributed On-Chip Power Management,” Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 532–540, November 2019.

[C13] D. Pathak and I. Savidis. “Evolving On-Chip Power Delivery through Particle Swarm Optimization,” Proceedings of the ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), pp. 1–6, September 2019.

[C12] H. Sayadi, D. Pathak, I. Savidis, and H. Homayoun “Power Conversion Efficiency-Aware Mapping of Multithreaded Applications on Heterogeneous Architectures: A Comprehensive Parameter Tuning”, Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018.

[C11] D. Pathak, H. Homayoun, and I. Savidis, “Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery”, Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 387–392, May 2017.

[C10] P. Chuang, C. Vezyrtzis, D. Pathak, R. Rizzolo, T. Webel, T. Strach, O.Torreiter, P. Lobo, A. Buyuktosunoglu, R. Bertran, M. Floyd, M. Ware, G. Salem, S. Carey, P. Restle, “Power Supply Noise in a 22nm z13TM Microprocessor,” Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), pp. 438–439, February 2017.

[C9] D. Pathak, M. Hajkazemi, M. Tavana, H. Homayoun, and I. Savidis, “Load Balanced On-Chip Power Delivery for Average Current Demand”, Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 439–444, May 2016.

[C8] D. Pathak, M. Hajkazemi, M. Tavana, H. Homayoun, and I. Savidis, “Energy Efficient On-Chip Power Delivery with Run-Time Voltage Regulator Clustering”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1210–1213, May 2016.

[C7] M. Tavana, D. Pathak, M. Hajkazemi, M. Malik, I. Savidis, and H. Homayoun, “Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping,” Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 581–588, October 2015.

[C6] M. Tavana, M. Hajkazemi, D. Pathak, I. Savidis, and H. Homayoun, “ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling,” Proceedings of the 52nd ACM Design Automation Conference (DAC), pp. 151–157, June 2015.

[C5] D. Pathak and I. Savidis. “Run-Time Voltage Detection Circuit for 3-D IC Power Delivery,” Proceedings of the IEEE 27th International SoC Conference (SoCC), pp. 183–187, September 2014.

[C4] D. Pathak and I. Savidis, “Power Supply Voltage Detection and Clamping Circuit for 3-D Integrated Circuits,” Proceedings of the IEEE SOI-3D- Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 94–96, October 2014.

[C3] D. Pathak and A. Kumar, “Design and Development of Wide Band Linear Phase Slanted IDT SAW Filter,” presented at 3rd International Conference on Microwave, Antenna, Propagation and Remote sensing, December 2006.

[C2] A. Kumar and D. Pathak, “SAWDevices for GAGAN Payload,” presented at ISRO Intercentre technical seminar, November 2005, ISRO Satellite Centre, India.

[C1] J. P. Pabari, H. Dave, V. Sinha, D. Balasubramaniyam, A. B. Shah, A. Dubey, N. M. Vadher, V. Shah, S. Thampi, R. P. Singh, V. Kumar, A. Kumar, and D. Pathak, “Chirp Transform Spectrometer Development for Submillimeter Wave Spectroscopy,” Proceedings of International Conference on Sub millimeter Science and Technology (ICSST), pp. 82–85, October 2004.

Patents

[P5] P. Chuang, D. Pathak, P. Restle, and, C. Vezyrtzis, “Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors,” U.S. Patent No. 10,437,311.

[P4] I. Savidis and D. Pathak, “Power Supply Voltage Detection and Power Delivery Circuit,” U.S. Patent No. 9,912,325.

[P3] I. Savidis, D. Pathak, and, H. Homayoun, “Work load scheduling for multi core systems with underprovisioned power delivery,”  US Patent Application Publication No. 2018/0314308 A1.

[P2] D. Pathak and I. Savidis, “On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors,” U.S. Patent Application No. 62,688,022.

[P1] D. Pathak and I. Savidis, “On-Chip Voltage Assignment through Particle Swarm Optimization,” U.S. Patent Application No. 62,726,345.

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Academic Honors

  • Ph.D. thesis selected for presentation at the 2019 ACM SIGDA and IEEE CEDA Ph.D. Forum, Design Automation Conference (DAC), Las Vegas, June 2019.
  • Awarded the 2017 IEEE Circuits and Systems Society Pre-Doctoral Scholarship. This is an international award with two recipients world wide per year.
  • Awarded the 2017 National Science Foundation (NSF) Professional Development Award as part of the iREDEFINE program (NSF Grant number 1663249).
  • Recipient of the Joseph and Shirley Carleone Endowed Fellowship, College of Engineering, Drexel University, 2017-2018.
  • Recipient of the Allen Rothwarf Scholarship, Department of Electrical and Computer Engineering, Drexel University, 2016-2017.
  • Awarded the 2016 IEEE Circuits and Systems Society Student Travel Award and the International Travel Award from Drexel University to present paper at ISCAS 2016 in Montreal, Canada.
  • Recipient of the Seaman Fellowship, Department of Electrical and Computer Engineering, Drexel University, 2014-2015.
  • Awarded membership due to superior academic record of IEEE Eta Kappa Nu (HKN), the IEEE honor society.
  • Qualified Graduate Aptitude Test in Engineering (GATE) in ECE discipline with 98.19 percentile.
  • Indian Air Force Benevolent Association (IAFBA) Scholarship holder, six year award from 10th grade to Senior year of college.

Academic Services

  • Reviewer for IEEE Transactions on Very Large Scale Integration  Systems (TVLSI)
  • Reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • Reviewer for Microelectronics Journal (MEJ)
  • Reviewer for IEEE International Symposium on Circuits and Systems (ISCAS), 2017 and 2018
  • Reviewer for IEEE Great Lakes VLSI Symposium (GLSVLSI), 2016, 2017, and 2018
  • Reviewer for IEEE/ACM International Conference On Computer Aided Design (ICCAD) 2018