Vaibhav is a Ph.D. student focusing on circuit level techniques to protect analog IP from intellectual property theft and counterfeiting. His Ph.D also focuses on variation aware automation of analog circuit design to reduce design time by minimizing iterations. He have experience in designing analog and custom integrated circuits and EDA tools. Vaibhav received his M.Sc. degree in computer engineering from Drexel University, PA, USA, in 2017.
Publications
[1] V.V. Rao and I. Savidis, “Protecting Analog Circuits with Parameter Biasing Obfuscation”, Proceedings of the 18th IEEE Latin American Test Symposium (LATS) , 1–6, March
2017
[2] V.V. Rao and I. Savidis Parameter, “Biasing Obfuscation for Analog IP”, Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST) , 161–161, May 2017
[3] V.V. Rao and I. Savidis, “Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory.”, Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 102–106, October 2018
[4] V. V. Rao and I. Savidis, “Mesh Based Obfuscation of Analog Circuit Properties”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May, 2019.
[5] V. V. Rao, and I. Savidis, “Security Oriented Analog Circuit Design Using Satisfiability Modulo Theory Based Search Space Exploration”, Proceedings of the Government Microcircuit Applications&Critical Technology Conference (GoMACTech), March, 2018
[6] K.Juretus, V. V. Rao, and I. Savidis, “Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies”, Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 483-488, May, 2019
Patent
[1] V.V. Rao and I. Savidis, “Protecting Analog Circuits with Parameter Biasing Obfuscation”, US Patent 15918278 , Issued October 10, 2018
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