Karthik Sangaiah: Difference between revisions
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[[File:Karthik.JPG|200px|thumb|right|Karthik "Paco" Sangaiah]] | |||
==Education== | ==Education== | ||
'''Ph.D. in Computer Engineering, | '''Ph.D. in Computer Engineering, 2020 ''' <br> | ||
:[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania | :[http://ece.drexel.edu Drexel University], Philadelphia, Pennsylvania | ||
| Line 9: | Line 9: | ||
==Research Interests== | ==Research Interests== | ||
* | * Heterogeneous Computing | ||
* Computer Architecture | * Computer Architecture | ||
* | * High Performance Computing | ||
* | * Communication Interconnects | ||
==Curriculum Vitae== | ==Curriculum Vitae== | ||
[[media: | [[media:CV_Dec2020.pdf | Karthik Sangaiah CV (Dec. 2020)]] | ||
==Publications== | ==Publications== | ||
# K. Sangaiah and P. Nagvajara, "Variable fractional digital delay filter on reconfigurable hardware," in Proceedings of IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, | #Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoC: Processing in the Communication Layer", ''Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA)'', February 2020[ [[Media:HPCA-SnackNoC-Slides-animated-final.pdf | Slides ]] ]. | ||
# Nilakantan, S. | #A. Hankin, T. Shapira, K. Sangaiah, M. Lui, M. Hempstead, "Evaluation of Non-Volatile Memory based Last Level Cache given Modern Use Case Behavior", Proceedings of IEEE International Symposium on Workload Characterization (IISWC), Nov. 2019. | ||
#M. Lui, K. Sangaiah, M. Hempstead, and B. Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, Northern Ireland, April 2018. | |||
#K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 1, April 2018 [ [[Media:ST 2018.pdf | Pre-Print ]] ]. | |||
#K. Sangaiah, B. Taskin, and M. Hempstead, "Fast Multicore Simulation and Performance Analysis of HPC Applications with SynchroTrace", Boston Area Architecture (BARC) Workshop, January 2016. | |||
#K. Sangaiah, M. Hempstead and B. Taskin, “Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling”, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2015, pp. 365–372. | |||
#S. Nilakantan, K. Sangaiah, A. More, G. Salvador, B. Taskin, M. Hempstead, ”SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), 29-31 March 2015, pp. 278-287. | |||
#K. Sangaiah and P. Nagvajara, "Variable fractional digital delay filter on reconfigurable hardware," in Proceedings of IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, pp. 430-433. | |||
#S. Nilakantan, S. Annangi, N. Gulati, K. Sangaiah, M. Hempstead, "Evaluation of an accelerator architecture for Speckle Reducing Anisotropic Diffusion," Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011 Proceedings of the 14th International Conference on, 9-14 Oct. 2011, pp.185-194. | |||
==Teaching== | ==Teaching== | ||
* ECE- | * ECE-C301: Advanced Programming for Engineers (Fall 2017) | ||
* ECE-C304: | * ECE-C302: Digital Systems Projects (Fall 2013, Spring 2014, Fall 2017) | ||
* ECE-C304: Design with Microcontrollers (Winter 2014) | |||
* ECE-C355: Computer Architecture (Summer 2014, Winter 2017) | |||
* ECE 203: Programming for Engineers (Winter 2018) | |||
* ENGR 121: Computation Lab I (Fall 2017) | |||
<!--:Please refer to my [[Weekly Schedule]] to ask for an appointment--> | <!--:Please refer to my [[Weekly Schedule]] to ask for an appointment--> | ||
| Line 32: | Line 43: | ||
Department of ECE <br> | Department of ECE <br> | ||
Drexel University <br> | Drexel University <br> | ||
Bossone | Bossone 405 <br> | ||
Philadelphia, PA 19104 <br> | Philadelphia, PA 19104 <br> | ||
Latest revision as of 18:30, 30 December 2020
Education
Ph.D. in Computer Engineering, 2020
- Drexel University, Philadelphia, Pennsylvania
B.S. and M.S. in Computer Engineering, 2012
- Drexel University, Philadelphia, Pennsylvania
Research Interests
- Heterogeneous Computing
- Computer Architecture
- High Performance Computing
- Communication Interconnects
Curriculum Vitae
Karthik Sangaiah CV (Dec. 2020)
Publications
- Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, and Mark Hempstead, "SnackNoC: Processing in the Communication Layer", Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2020[ Slides ].
- A. Hankin, T. Shapira, K. Sangaiah, M. Lui, M. Hempstead, "Evaluation of Non-Volatile Memory based Last Level Cache given Modern Use Case Behavior", Proceedings of IEEE International Symposium on Workload Characterization (IISWC), Nov. 2019.
- M. Lui, K. Sangaiah, M. Hempstead, and B. Taskin, "Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces", Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, Northern Ireland, April 2018.
- K. Sangaiah, M. Lui, R. Jagtap, S. Diestelhorst, S. Nilakantan, A. More, B. Taskin, and M. Hempstead, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation of CMP and HPC Workloads", ACM Transactions on Architecture and Code Optimization (TACO), Volume 15, Issue 1, April 2018 [ Pre-Print ].
- K. Sangaiah, B. Taskin, and M. Hempstead, "Fast Multicore Simulation and Performance Analysis of HPC Applications with SynchroTrace", Boston Area Architecture (BARC) Workshop, January 2016.
- K. Sangaiah, M. Hempstead and B. Taskin, “Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling”, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2015, pp. 365–372.
- S. Nilakantan, K. Sangaiah, A. More, G. Salvador, B. Taskin, M. Hempstead, ”SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multi-core Simulation”, Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2015), 29-31 March 2015, pp. 278-287.
- K. Sangaiah and P. Nagvajara, "Variable fractional digital delay filter on reconfigurable hardware," in Proceedings of IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS 2012), 5-8 August 2012, pp. 430-433.
- S. Nilakantan, S. Annangi, N. Gulati, K. Sangaiah, M. Hempstead, "Evaluation of an accelerator architecture for Speckle Reducing Anisotropic Diffusion," Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011 Proceedings of the 14th International Conference on, 9-14 Oct. 2011, pp.185-194.
Teaching
- ECE-C301: Advanced Programming for Engineers (Fall 2017)
- ECE-C302: Digital Systems Projects (Fall 2013, Spring 2014, Fall 2017)
- ECE-C304: Design with Microcontrollers (Winter 2014)
- ECE-C355: Computer Architecture (Summer 2014, Winter 2017)
- ECE 203: Programming for Engineers (Winter 2018)
- ENGR 121: Computation Lab I (Fall 2017)
Contact Information
Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 405
Philadelphia, PA 19104
Email: ks499@drexel.edu
Linkedin: Karthik Sangaiah
