Can Sitik: Difference between revisions

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==Education==
==Education==
'''Ph.D. in Computer Engineering, 2011 - Present''' <br>  
'''Ph.D. in Computer Engineering, 2011 - 2015''' <br>  
:Drexel University, Philadelphia, Pennsylvania, USA
:Drexel University, Philadelphia, Pennsylvania, USA


Line 12: Line 12:


==Research Interests==
==Research Interests==
* High-Performance/Low-Power Clock Networks
* Low Swing Clock Tree Synthesis
* Low Swing Clock Trees
* Pre- and Post-Si Power and Timing Modeling
* Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]
* Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]
* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]
* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]
* Physical Design of System-on-Chips
* Clock Network Design with FinFETs


==Curriculum Vitae==
==Curriculum Vitae==
[[media:Can_CV.pdf | Can Sitik CV (Dec 2013)]]
[[media:Can_CV.pdf | Can Sitik CV (Feb 2015)]]


==Publications==
==Publications==
# Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", to appear in ''Elsevier Integration, the VLSI Journal'', November 2013.
 
# Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", to appear in the ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013.
====Journals====
# Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.
# C. Sitik, W. Liu, B. Taskin and E. Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", (accepted to) ''IEEE Transactions on Very Large Scale Integration Systems (TVLSI)'', January 2016.
# Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.
# C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ''ACM Journal of Emerging Technologies in Computing Systems (JETC)'', Vol. 12, No. 2, Article 13, August 2015.
# Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.
# C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", ''Elsevier Integration, The VLSI Journal'', Vol. 47, No. 3, pp. 356--364, June 2014.
# Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.
 
====Conferences====
# W. Liu, E. Salman, C. Sitik and B. Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", to appear in ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.
#W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
#M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings  of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.
#W. Liu, E. Salman, C. Sitik and B. Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", ''Proceedings  of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 283--288.
#W. Liu, E. Salman, C. Sitik and B. Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2015, pp. 1442--1445.
# C. Sitik, S. Lerner and B. Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2014, pp. 230--236.
# C. Sitik, L. Filippini, E. Salman and B. Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", ''Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)'', July 2014, pp. 498--503.
# C. Sitik, P. Nagvajara and B. Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", ''Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE)'', June 2013, pp. 28--31.
# C. Sitik and B. Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 209--214.
# C. Sitik and B. Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", ''Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2013, pp. 49--54 '''Best Paper Nominee'''.
# C. Sitik and B. Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", ''Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley'', March 2013.
# C. Sitik and B. Taskin, "Multi-Voltage Domain Clock Mesh Design", ''Proceedings of the IEEE International Conference on Computer Design (ICCD)'', October 2012, pp. 201--206.
[http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&hl=en '''Google Scholar Page''']
[http://scholar.google.com/citations?user=ZwNZgjAAAAAJ&hl=en '''Google Scholar Page''']


==Teaching==
==Teaching==
* ECE-C671: EDA for VLSI I (Winter 2015)
* ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)
* ECE-C304: [http://ece.drexel.edu/courses/ECE-C304/ Design with Microcontrollers] (Winter 2012-14, Summer 2012,13)
* ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)
* ECE-C302: [http://ece.drexel.edu/courses/ECE-C302/ Digital Systems Projects] (Fall, Spring 2013)
* ENGR-231: Linear Engineering Systems (Spring, Fall 2012)
* ENGR-231: Linear Engineering Systems (Spring, Fall 2012)
* ECE-E421: Advanced Electronics I (Fall 2011)
* ECE-E421: [http://www.ece.drexel.edu/courses/ECE-E421/ Advanced Electronics I] (Fall 2011)
:Please refer to my [[Weekly Schedule]] to ask for an appointment
:Please refer to my [[Weekly Schedule]] to ask for an appointment


==Contact Information==
==Contact Information==
'''Address:''' <br>
'''Address:''' <br>
3141 Chestnut Street <br>
Hillsboro, OR 97124 <br>
Department of ECE <br>
Drexel University <br>
Bossone 324 <br>
Philadelphia, PA 19104 <br>


'''Email:''' [mailto:as3577@drexel.edu as3577@drexel.edu] <br>
'''Email:''' [mailto:cansitik@gmail.com cansitik@gmail.com] <br>


'''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&trk=hb_tab_pro_top A. Can Sitik]
'''Linkedin:''' [http://www.linkedin.com/profile/view?id=147018021&trk=hb_tab_pro_top A. Can Sitik]

Latest revision as of 02:11, 7 March 2016

Can Sitik

Education

Ph.D. in Computer Engineering, 2011 - 2015

Drexel University, Philadelphia, Pennsylvania, USA

M.S. in Computer Engineering, 2013

Drexel University, Philadelphia, Pennsylvania, USA

B.S. in Electrical and Electronics Engineering, 2011

Middle East Technical University(METU), Ankara, Turkey

Research Interests

  • Low Swing Clock Tree Synthesis
  • Pre- and Post-Si Power and Timing Modeling
  • Clock Mesh Synthesis, clock mesh benefits
  • Electronic Design Automation(EDA) for VLSI, what is EDA?
  • Clock Network Design with FinFETs

Curriculum Vitae

Can Sitik CV (Feb 2015)

Publications

Journals

  1. C. Sitik, W. Liu, B. Taskin and E. Salman, "Design Methodology for Voltage-Scaled Clock Distribution Networks", (accepted to) IEEE Transactions on Very Large Scale Integration Systems (TVLSI), January 2016.
  2. C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 12, No. 2, Article 13, August 2015.
  3. C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", Elsevier Integration, The VLSI Journal, Vol. 47, No. 3, pp. 356--364, June 2014.

Conferences

  1. W. Liu, E. Salman, C. Sitik and B. Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", to appear in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2016.
  2. W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", Proceedings of Semiconductor Research Corporation (SRC) TECHCON, September 2015.
  3. M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 301--306.
  4. W. Liu, E. Salman, C. Sitik and B. Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 283--288.
  5. W. Liu, E. Salman, C. Sitik and B. Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, pp. 1442--1445.
  6. C. Sitik, S. Lerner and B. Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2014, pp. 230--236.
  7. C. Sitik, L. Filippini, E. Salman and B. Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014, pp. 498--503.
  8. C. Sitik, P. Nagvajara and B. Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2013, pp. 28--31.
  9. C. Sitik and B. Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 209--214.
  10. C. Sitik and B. Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 49--54 Best Paper Nominee.
  11. C. Sitik and B. Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley, March 2013.
  12. C. Sitik and B. Taskin, "Multi-Voltage Domain Clock Mesh Design", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 201--206.

Google Scholar Page

Teaching

Please refer to my Weekly Schedule to ask for an appointment

Contact Information

Address:
Hillsboro, OR 97124

Email: cansitik@gmail.com

Linkedin: A. Can Sitik

Retrieved from "https://research.coe.drexel.edu/ece/vlsi/index.php?title=Can_Sitik&oldid=1472"